VDCC based dual-mode quadrature sinusoidal oscillator with outputs at appropriate impedance levels

This article presents a new dual-mode (i.e. both current-mode and voltage-mode) quadrature sinusoidal oscillator using two Voltage Differencing Current Conveyors (VDCCs), two resistors and two capacitors. The proposed configuration use only grounded passive elements and enjoys independent resistor/electronic tuning of both Condition of Oscillation (CO) as well as Frequency of Oscillation (FO). The quadrature current and voltage mode outputs of this circuit are available at appropriate impedance terminals. The behavior of presented oscillator is also examined under non ideal/parasitic conditions. The validity of the proposed configuration has been confirmed by SPICE simulations with TSMC 0.18μm process parameters

An Explicit Output Current-mode Quadrature Sinusoidal Oscillator and a Universal Filter Employing Only Grounded Passive Components - a Minimal Realisation

The use of voltage differencing current conveyor as an active device to design a current-mode oscillator along with a universal filter with only grounded passive elements is the main focus of this manuscript. This re-arranging circuit can work as a sinusoidal oscillator as well as a current-mode universal filter, by simple selection of passive switches. Both the circuits employ only two active devices and three grounded passive elements. The designed oscillator provides two distinctive current outputs with a quadrature-phase difference. It also maintains an independent condition of oscillation and frequency of oscillation. Moreover, the basic responses including low pass, high pass, and band pass are easily available from a current-mode universal filter. The low input impedance and high output impedance are amongst the noteworthy features of the current-mode derived filter. Non-ideal, parasitic, and sensitivity analysis of the designed circuits are also incorporated in the manuscript. Cadence PSPICE software simulation results are also included to justify the design idea. Experimental implementation of the described circuit has also been shown by employing special-purpose amplifier integrated circuit, i.e., OPA860

One input voltage and three output voltage universal biquad filters with orthogonal tune of frequency and bandwidth

This research paper contributes the one input three output voltage mode universal biquad filters with linear and electronic control of the natural frequency (w0), using two commercially available ICs, LT1228s as active device with two grounded capacitors, five resistors. The presented universal biquad filters can simultaneously provide three voltage-mode filtering functions, low-pass (LP), high-pass (HP) and band-pass (BP) without changing the circuit architecture. Furthermore, the first presented biquad filter provides low impedance at HP, BP voltage output nodes and LP, BP output voltage nodes are low impedance for the second proposed filter which is easy cascade ability with other voltage mode circuits without the employment of buffer circuits. The quality factor (Q) of both proposed filters is orthogonally adjusted from the passband voltage gain and w0. The proposed filters are simulated and experimented with commercially accessible ICs, LT1228. The simulated and experimental results demonstrate the filtering performances

Advanced characterisation techniques for envelope tracking power amplifiers

Envelope tracking (ET) is a strong contender architecture for enhancing the power efficiency performance of power amplifiers (PAs) in emerging communication systems. However, the design and characterisation of envelope tracking power amplifiers (ET-PAs) introduces a number of significant technical challenges related to the optimisation and interaction of the numerous subsystems involved, namely the PA itself, envelope detection/generation, the supply modulator and linearisation elements. This Ph.D. research extends the current state of the art in ET-PA measurement and characterisation and considers new measurement and characterisation capabilities that provide for the rapid development of ET-PA architectures. The research starts by fully implementing a new ET-PA measurement system and includes the characterisation and validation of the requirements for such a system. Following this, the realised system is used to investigate the important area of interaction between an PA and a supply modulator in the presence of voltage ripple representative of an actual switching modulator. By varying the ripple magnitude as a proportion of the modulated drain voltage, the effects on the linearity of the PA are observed and analysed, providing the system designer with insight into the amount of ripple that is tolerable, and at what cost in terms of other key parameters. Additionally, potential countermeasures including digital pre-distortion (DPD) and shaping function optimisation are explored and the influence of the ripple magnitude on an ET-PA is quantified. The second part of the thesis presents an integration of a modulated active load-pull system, allowing simultaneous broadband impedance environment emulation and DPD linearisation, in one integrated measurement system. This novel combination allows investigation of for example, how well a microwave power transistor, operating in an optimal RF impedance environment, responds to linearisation with DPD techniques. Following this demonstration, a fully emulated ET-PA environment is realised by adding a dynamic supply voltage capability, and excited using industry-standard modulated. As a result, a measurement setup has been demonstrated that enables the PA designer to characterise device operation within fully emulated PA modes of operation, under realistic modulated signal conditions, as well as allowing, in real time, the rapid investigation into how well these modes respond simultaneously to ET and DPD techniques

A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation

Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop accordingly to meet the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices. Specically this entails meeting stringent noise specications imposed by modern wireless standards, meeting low power consumption budgets to prolong battery lifetimes, operating under reduced supply voltages imposed by modern technology nodes and within the noisy environments of complex system-on-chip (SOC) designs, all in addition to consuming as little silicon area as possible. The ability of the PLL to achieve the above is thus key to its continual progress in enabling wireless technology achieve increasingly powerful products which increasingly benet our daily lives. This thesis furthers the development of PLLs with respect to meeting the challenges imposed upon it by modern wireless technology, in two ways. Firstly, the thesis describes in detail the advantages to be gained through employing a fully dierential PLL. Specically, such PLLs are shown to achieve low noise performance, consume less silicon area than their conventional counterparts whilst consuming similar power, and being better suited to the low supply voltages imposed by continual technology downsizing. Secondly, the thesis proposes a sub-banded VCO architecture which, in addition to satisfying simultaneous requirements for large tuning ranges and low phase noise, achieves signicant reductions in PLL loop bandwidth variation. First and foremost, this improves on the stability of the PLL in addition to improving its dynamic locking behaviour whilst oering further improvements in overall noise performance. Since the proposed sub-banded architecture requires no additional power over a conventional sub-banded architecture, the solution thus remains attractive to the realm of low power design. These two developments combine to form a fully dierential PLL with reduced loop bandwidth variation. As such, the resulting PLL is well suited to meeting the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices, and thus applicable to the continual development of wireless technology in benetting our daily lives

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine