The Octopus switch

This chapter1 discusses the interconnection architecture of the Mobile Digital Companion. The approach to build a low-power handheld multimedia computer presented here is to have autonomous, reconfigurable modules such as network, video and audio devices, interconnected by a switch rather than by a bus, and to offload as much as work as possible from the CPU to programmable modules placed in the data streams. Thus, communication between components is not broadcast over a bus but delivered exactly where it is needed, work is carried out where the data passes through, bypassing the memory. The amount of buffering is minimised, and if it is required at all, it is placed right on the data path, where it is needed. A reconfigurable internal communication network switch called Octopus exploits locality of reference and eliminates wasteful data copies. The switch is implemented as a simplified ATM switch and provides Quality of Service guarantees and enough bandwidth for multimedia applications. We have built a testbed of the architecture, of which we will present performance and energy consumption characteristics

SIMULATIVE ANALYSIS OF ROUTING AND LINK ALLOCATION STRATEGIES IN ATM NETWORKS

For Broadband Integrated Services Digital (B-ISDN) networks ATM is a promising technology, because it supports a wide range of services with different bandwidth demands, traffic characteristics and QoS requirements. This diversity of services makes traffic control in these networks much more complicated than in existing circuit or packet switched networks. Traffic control procedures include both actions necessary for setting up virtual connections (VC), such as bandwidth assignment, call admission, routing and resource allocation and congestion control measures necessary to maintain throughput in overload situations. This paper deals with routing and link allocation, and analyses the performance of such algorithms in terms of call blocking probability, link capacity utilization and QoS parameters. In our model the network carries out the following steps when a call is offered to the network: (1) Assign an appropriate bandwidth to an offered call (Bandwidth assignment) (2) Find a transmission path between the source and destination with enough available transmission capacity (Routing) (3) Allocate resource along that path (Link allocation) We consider an example 5-node network [7], conduct an extensive survey of routing, and link allocation algorithms. Regarding step (1) we employ the equivalent link capacity assignment presented by various interesting papers [1]-[5]. We find that the choice of routing and link allocation algorithms has a great impact on network performance, and that different routing algorithms perform best under different network load values. Shortest path routing (SPR) is a good candidate for low, alternate routing (AR) for medium and non-alternate routing (NAR) for high traffic load values. Concerning link allocation strategies, we find that partial overlap (POL) strategies that seem to be able to present near optimal performance are superior to complete sharing (CS) and complete partitioning (CP) strategies. As a further improvement of the POL scheme, we propose a 2-level link allocation algorithm, which yields highest link utilization. In this scheme, not only the accesses of different service classes to different virtual paths (VPs) are controlled, but also an individual VP's transmission capacity is optimally allocated to the service classes according to their bandwidth requirements in order to assure high link utilization. This method seems to be adjustable to the fine degree of granularity of bandwidth demands in B-ISDN networks. It is shown that in order to minimize cell loss the call level resource allocation plays a significant role: networks with the same buffer size switches display different cell loss probabilities in the nodes and impose different end-to-end delay on cells if the link allocation and routing differ. Again, we find that when traffic is tolerable by the network, SPR causes the least cell loss. This can be explained by the fact that SPR spreads the incoming calls in the network. It eagerly seeks new routes instead of utilizing the already used but still not congested routes. SPR obviously wastes more rapidly link and buffer capacity as traffic load becomes higher than the AR, which chooses a new route only when it has to, i.e. when the route of higher priority becomes congested. That is why we experience that as soon as the SPR starts loosing cells, it indicates that available resources have been consumed and it rapidly goes up to very high blocking probabilities after a small further increase of load

BMSN and SpiderNet as large scale ATM switch interconnection architectures.

by Kin-Yu Cheung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 64-[68]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Multistage Interconnection Architectures --- p.2Chapter 1.2 --- Interconnection Topologies --- p.4Chapter 1.3 --- Design of Switch Module-An Example of Multichannel Switch --- p.7Chapter 1.4 --- Organization --- p.8Chapter 1.5 --- Publication --- p.9Chapter 2 --- BMSN and SpiderNet: Two Large Scale ATM Switches --- p.13Chapter 2.1 --- Introduction --- p.13Chapter 2.2 --- Architecture --- p.14Chapter 2.2.1 --- Topology --- p.14Chapter 2.2.2 --- Switch Modules --- p.15Chapter 2.3 --- Routing --- p.17Chapter 2.3.1 --- VP/VC Routing --- p.18Chapter 2.3.2 --- VP/VC Routing Control --- p.22Chapter 2.3.3 --- Cell Routing --- p.23Chapter 2.3.4 --- Alternate Path Routing for Fault Tolerance --- p.24Chapter 2.4 --- SpiderNet --- p.25Chapter 2.5 --- Performance and Discussion --- p.26Chapter 2.5.1 --- BMSN vs SpiderNet --- p.26Chapter 2.5.2 --- Network Capacity --- p.29Chapter 2.6 --- Concluding Remarks --- p.30Chapter 3 --- Multichannel ATM Switching --- p.39Chapter 3.1 --- Introduction --- p.39Chapter 3.2 --- Switch Design --- p.40Chapter 3.3 --- Channel Allocation Algorithms --- p.41Chapter 3.3.1 --- VC-Based String Round Robin (VCB-SRR) Algorithm --- p.41Chapter 3.3.2 --- Implementation of the VCB-SRR Algorithm --- p.43Chapter 3.3.3 --- Channel Group Based Round Robin (CGB-RR) Algorithm --- p.50Chapter 3.3.4 --- Implementation of the CGB-RR Algorithm --- p.51Chapter 3.4 --- Performance and Discussion --- p.53Chapter 3.5 --- Concluding Remarks --- p.57Chapter 4 --- Conclusion --- p.62Bibliography --- p.6

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

Switching techniques in data-acquisition systems for future experiments

An overview of the current state of development of parallel event-building techniques is given, with emphasis of future applications in the high-rate experiments proposed at the Large Hadron Collider (LHC). The paper describes the ain architectural options in parallel event builders, the proposed event-building architectures for LHC experiments, and the use of standard net- working protocols for event building and their limitations. The main issues around the potential use of circuit switching, message switching and packet switching are examined. Results from various laboratory demonstrator systems are presented

Traffic grooming and wavelength conversion in optical networks

Wavelength Division Multiplexing (WDM) using wavelength routing has emerged as the dominant technology for use in wide area and metropolitan area networks. Traffic demands in networks today are characterized by dynamic, heterogeneous flows. While each wavelength has transmission capacity at gigabit per second rates, users require connections at rates that are lower than the full wavelength capacity. In this thesis, we explore network design and operation methodologies to improve the network utilization and blocking performance of wavelength routing networks which employ a layered architecture with electronic and optical switching. First we provide an introduction to first generation SONET/SDH networks and wavelength routing networks, which employ optical crossconnects. We explain the need and role of wavelength conversion in optical networks and present an algorithm to optimally place wavelength conversion devices at the network nodes so as to optimize blocking performance. Our algorithm offers significant savings in computation time when compared to the exhaustive method.;To make the network viable and cost-effective, it must be able to offer sub-wavelength services and be able to pack these services efficiently onto wavelengths. The act of multiplexing, demultiplexing and switching of sub-wavelength services onto wavelengths is defined as traffic grooming. Constrained grooming networks perform grooming only at the network edge. Sparse grooming networks perform grooming at the network edge and the core. We study and compare the effect of traffic grooming on blocking performance in such networks through simulations and analyses. We also study the issue of capacity fairness in such networks and develop a connection admission control (CAC) algorithm to improve the fairness among connections with different capacities. We finally address the issues involved in dynamic routing and wavelength assignment in survivable WDM grooming networks. We develop two schemes for grooming primary and backup traffic streams onto wavelengths: Mixed Primary-Backup Grooming Policy (MGP) and Segregated Primary-Backup Grooming Policy (SGP). MGP is useful in topologies such as ring, characterized by low connectivity and high load correlation and SGP is useful in topologies, such as mesh-torus, with good connectivity and a significant amount of traffic switching and mixing at the nodes

Simulation and analytical performance studies of generic atm switch fabrics.

As technology improves exciting new services such as video phone become possible and economically viable but their deployment is hampered by the inability of the present networks to carry them. The long term vision is to have a single network able to carry all present and future services. Asynchronous Transfer Mode, ATM, is the versatile new packet -based switching and multiplexing technique proposed for the single network. Interest in ATM is currently high as both industrial and academic institutions strive to understand more about the technique. Using both simulation and analysis, this research has investigated how the performance of ATM switches is affected by architectural variations in the switch fabric design and how the stochastic nature of ATM affects the timing of constant bit rate services. As a result the research has contributed new ATM switch performance data, a general purpose ATM switch simulator and analytic models that further research may utilise and has uncovered a significant timing problem of the ATM technique. The thesis will also be of interest and assistance to anyone planning on using simulation as a research tool to model an ATM switch

A Performance evaluation of several ATM switching architectures

The goal of this thesis is to evaluate the performance of three Asynchronous Transfer Mode switching architectures. After examining many different ATM switching architectures in literature, the three architectures chosen for study were the Knockout switch, the Sunshine switch, and the Helical switch. A discrete-time, event driven system simulator, named ProModel, was used to model the switching behavior of these architectures. Each switching architecture was modeled and studied under at least two design configurations. The performance of the three architectures was then investigated under three different traffic types representative of traffic found in B-ISDN: random, constant bit rate, and bursty. Several key performance parameters were measured and compared between the architectures. This thesis also explored the implementation complexities and fault tolerance of the three selected architectures