Electromagnetic compatibility of CMOS circuits along the lifetime

The continuous scaling of CMOS circuits has set the MOSFET transistor in the nanoelectronic era. In this context, the functionality and complexity of integrated circuits (ICs) are growing up. However, the operation voltage has been continuously reduced. The higher complexity of ICs has allowed including electronic systems in a lot of safety critical applications (i.e., automotive, aeronautics and/or medical applications). Therefore, the functionality of these electronic equipments must be assured and the risk of electromagnetic interference (EMI) must be reduced during their lifetime. Nowadays, circuits’ robustness to electromagnetic interference is checked in a burn-in component, without taking into account the impact of the natural devices’ aging. However, shrunk dimensions imply the appearance of several wear out mechanisms, which can limit the functionality of the circuits and modify their electromagnetic performance. Therefore, the time dependence of electromagnetic behaviour, which is known as Electromagnetic Robustness or Electromagnetic Reliability (EMR), should be evaluated. The switching noise is probably one of the main EMC emission problems in CMOS circuits. It is know that wear out mechanism affects the switching behaviour of CMOS circuits. Therefore, some effects on EMC performance of these circuits should be expected. In this work, the switching noise behaviour or CMOS circuits under one of the most important reliability problems are analysed by means of electrical simulation. In order to do that, a characterization of wear out mechanism on single MOSFET is presented and modelled. The results show a reduction on the frequency switching noise emission in circuits subjected to wear out, due to the reduction of the drain current of MOSFET.Peer ReviewedPostprint (published version

VeriSFQ - A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology

In this paper, we propose a semi-formal verification framework for single-flux quantum (SFQ) circuits called VeriSFQ, using the Universal Verification Methodology (UVM) standard. The considered SFQ technology is superconducting digital electronic devices that operate at cryogenic temperatures with active circuit elements called the Josephson junction, which operate at high switching speeds and low switching energy - allowing SFQ circuits to operate at frequencies over 300 gigahertz. Due to key differences between SFQ and CMOS logic, verification techniques for the former are not as advanced as the latter. Thus, it is crucial to develop efficient verification techniques as the complexity of SFQ circuits scales. The VeriSFQ framework focuses on verifying the key circuit and gate-level properties of SFQ logic: fanout, gate-level pipeline, path balancing, and input-to-output latency. The combinational circuits considered in analyzing the performance of VeriSFQ are: Kogge-Stone adders (KSA), array multipliers, integer dividers, and select ISCAS'85 combinational benchmark circuits. Methods of introducing bugs into SFQ circuit designs for verification detection were experimented with - including stuck-at faults, fanout errors, unbalanced paths, and functional bugs like incorrect logic gates. In addition, we propose an SFQ verification benchmark consisting of combinational SFQ circuits that exemplify SFQ logic properties and present the performance of the VeriSFQ framework on these benchmark circuits. The portability and reusability of the UVM standard allows the VeriSFQ framework to serve as a foundation for future SFQ semi-formal verification techniques.Comment: 7 pages, 6 figures, 4 tables; submitted, accepted, and presented at ISQED 2019 (20th International Symposium on Quality Electronic Design) on March 7th, 2019 in Santa Clara, CA, US

Superconducting electronics

During the last decades superconducting electronics has been the most prominent area of research for small scale applications of superconductivity. It has experienced quite a stormy development, from individual low frequency devices to devices with high integration density and pico second switching time. Nowadays it offers small losses, high speed and the potential for large scale integration and is superior to semiconducting devices in many ways ¿ apart from the need for cooling by liquid helium for devices based on classical superconductors like niobium, or cooling by liquid nitrogen or cryocoolers (40K to 77K) for high-Tc superconductors like YBa2Cu3O7. This article gives a short overview over the current state of the art on typical devices out of the main application areas of superconducting electronics

Investigations on electromagnetic noises and interactions in electronic architectures : a tutorial case on a mobile system

Electromagnetic interactions become critic in embedded and smart electronic structures. The increase of electronic performances confined in a finite volume or support for mobile applications defines new electromagnetic environment and compatibility configurations (EMC). With canonical demonstrators developed for tutorials and EMC experiences, this paper present basic principles and experimental techniques to investigate and control these severe interferences. Some issues are reviewed to present actual and future scientific challenges for EMC at electronic circuit level

Teaching Memory Circuit Elements via Experiment-Based Learning

The class of memory circuit elements which comprises memristive, memcapacitive, and meminductive systems, is gaining considerable attention in a broad range of disciplines. This is due to the enormous flexibility these elements provide in solving diverse problems in analog/neuromorphic and digital/quantum computation; the possibility to use them in an integrated computing-memory paradigm, massively-parallel solution of different optimization problems, learning, neural networks, etc. The time is therefore ripe to introduce these elements to the next generation of physicists and engineers with appropriate teaching tools that can be easily implemented in undergraduate teaching laboratories. In this paper, we suggest the use of easy-to-build emulators to provide a hands-on experience for the students to learn the fundamental properties and realize several applications of these memelements. We provide explicit examples of problems that could be tackled with these emulators that range in difficulty from the demonstration of the basic properties of memristive, memcapacitive, and meminductive systems to logic/computation and cross-bar memory. The emulators can be built from off-the-shelf components, with a total cost of a few tens of dollars, thus providing a relatively inexpensive platform for the implementation of these exercises in the classroom. We anticipate that this experiment-based learning can be easily adopted and expanded by the instructors with many more case studies.Comment: IEEE Circuits and Systems Magazine (in press

An emerging paradigm or just another trajectory? Understanding the nature of technological changes using engineering heuristics in the telecommunications switching industry

The theoretical literature on technological changes distinguishes between paradigmatic changes and changes in trajectories. Recently several scholars have performed empirical studies on the way technological trajectories evolve in specific industries, often by predominantly looking at the artifacts. Much less - if any - empirical work has been done on paradigmatic changes, even though these have a much more profound impact on today's industry. It follows from the theory that such studies would need to focus more on the knowledge level than on the artifact level, raising questions on how to operationalize such phenomena. This study aims to fill this gap by applying network-based methodologies to knowledge networks, represented here by patents and patent citations. The rich technological history of telecommunications switches shows how engineers in the post-war period were confronted with huge challenges to meet drastically changing demands. This historical background is a starting point for an in-depth analysis of patents, in search of information about technological direction, technical bottlenecks, and engineering heuristics. We aim to identify when such changes took place over the seven different generations of technological advances this industry has seen. In this way we can easily recognize genuine paradigmatic changes compared to more regular changes in trajectory.technological trajectories; patents; network analysis; telecommunication manufacturing industry