Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology

In the present work, a CMOS ternary to binary bit conversion technique has been proposed using multiple input floating gate MOSFETs. The proposed circuit has been implemented in 0.5 µm n-well CMOS technology. The ternary input signals of {-1, 0, +1} are represented as -3 V, 0 V and +3 V, respectively. The ternary input is given as a combination of any two of the three voltage levels and the 4-bit binary output is generated in which the left most bit is sign bit (SB) followed by most significant bit (MSB), second significant bit (SSB) and the least significant bit (LSB). The potential on the floating gate can be modified by either capacitive coupling with other conductors or by changing the stored charge on the floating gate. After each computation for a certain combination of inputs the floating gate carries a specific charge which has to be removed, or compensated for in order, to maintain integrity of the next computation. The four methods used commonly for modifying stored charge on the floating gate are UV radiation, tunneling, channel hot-electron injection and hopping through or trapping/de-trapping of charges. A simple method has been presented where the residual charge on the floating gate is by-passed and set to a certain biased initial value. Based on this initial value for the floating node voltage, the ratios of the values of the input capacitors which are capacitively coupled to the floating gate have been designed. The design was simulated in PSPICE and the output voltage at each stage of the converter was used to back calculate and model the ratios for the input capacitors as well as determine the biasing voltage on the floating gate

Ternary and quaternary logic to binary bit conversion CMOS integrated circuit design using multiple input floating gate MOSFETs

Multiple-input floating gate MOSFETs and floating gate potential diagrams have been used for conversion of ternary-valued input and quaternary-valued input into corresponding binary-valued output in CMOS integrated circuit design environment. The method is demonstrated through the design of a circuit for conversion of ternary inputs 00 to -1-1 (decimal 0 to -4) and 00 to 11 (decimal 0 to +4) into the corresponding binary bits and for conversion of quaternary inputs (decimal 0 to 3) into the corresponding binary bits (binary 00 to 11) in a standard 1.5 mm digital CMOS technology. The physical design of the circuits is simulated and tested with SPICE using MOSIS BSIM3 model parameters. The conversion method is simple and compatible with the present CMOS process. The circuits could be embedded in digital CMOS VLSI design architectures. The conversion circuit for ternary inputs into corresponding binary outputs has maximum propagation delay of 8 ns with 0.1 pF simulated capacitive load. The physical layout design occupies an area of 432´908 mm2. The conversion circuit for quaternary inputs to corresponding binary outputs has maximum propagation delay of 6 ns with 0.1 pF simulated capacitive load. The physical layout design occupies an area of 130´175 mm2. The conversion circuit achieved significant improvement in the number of devices. A reduction of more than 75% in transistor count was obtained over the previous designs. Measurements of the fabricated devices for the conversion of quaternary input into binary output agree with simulated values