49,491 research outputs found

    The Backstroke framework for source level reverse computation applied to parallel discrete event simulation

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    This report introduces Backstroke, a new open source framework for the automatic generation of reverse code for functions written in C++. Backstroke enables reverse computation for optimistic parallel discrete event simulations. It is built over the ROSE open- source compiler infrastructure, and handles complex C++ features including pointers and pointer types, arrays, function and method calls, class types. inheritance, polymorphism, virtual functions, abstract classes, templated classes and containers. Backstroke also introduces new program inversion techniques based on advanced compiler analysis tools built into ROSE. We explore and illustrate some of the complex language and semantic issues that arise in generating correct reverse code for C++ functions

    An extensible language for the generation of parallel data manipulation andcontrol packages

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    The design and implementation of the language fSDL (full Structure Definition Language) is discussed. In fSDL, complex user-defined data types such as lists, tables, trees, and graphs can be constructed from a tiny set of primitives. Beyond mere structure definitions (also offered by previously existing tools) high-level functionality on these data types can be specified. In the COMPARE (ESPRIT) project, the C code generated from an fSDL specification will be used by compiler-components running in parallel on a common data pool. fSDL is first translated into a sublanguage, flat fSDL, from which the actual C code is produced. Flat fSDL is a convenient interface for cooperation with other compiler generation tools. There is a formal relation between the input fSDL and the resulting flat form

    System level synthesis of dataflow programs: HEVC decoder case study

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    International audienceWhile dealing with increasing complexity of signal processing algorithms, the primary motivation for the development of High-Level Synthesis (HLS) tools for the automatic generation of Register Transfer Level (RTL) description from high-level description language is the reduction of time-to-market. However, most existing HLS tools operate at the component level, thus the entire system is not taken into consideration. We provide an original technique that raises the level of abstraction to the system level in order to obtain RTL description from a dataflow description. First, we design image processing algorithms using an actor oriented language under the Reconfigurable Video Coding (RVC) standard. Once the design is achieved, we use a dataflow compilation infrastructure called Open RVC-CAL Compiler (Orcc) to generate a C-based code. Afterward, a Xilinx HLS tool called Vivado is used for an automatic generation of synthesizable hardware implementation. In this paper, we show that a simulated hardware code generation of High Efficiency Video Coding (HEVC) under the RVC specifications is rapidly obtained with promising preliminary results

    Implementing the Factory Pattern with the Help of Reflection

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    Reflection, reflection-based programming and metaprogramming are valuable tools for many programming tasks, like the implementation of persistence and serialization-like operations, object-relational mapping, remote method invocation, automatic generation of user-interfaces, etc., and also for the implementation of several design patterns. C++ as one of the most prevalent programming languages still lacks support for standardised, compiler-assisted reflection. In this paper we introduce in short the Mirror reflection library which is a part of an ongoing effort to add reflection to C++ and we will show how reflection can be used to greatly simplify the implementation of object factories - classes constructing instances of other classes from various external data representations
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