Modeling and design of high speed SRAM based memory chip

SRAM is used as Cache memory which is very fast and used to speed up the task of processor and memory interface. With improvements in VLSI technology, processor speeds have increased. The improvements in SRAM speed of operation with increased integration, bigger sizes, technology shrinking and power dissipation is required to match with improved processor. 2kb SRAM block is designed and tested for proper read and write operation. The single SRAM cell, the 32x32 memory array, along with the decoder circuit, the sense enable and write enable logic, are placed out. The different critical paths of the system, comprising of the row and the column decoder, the column mux and the read-write circuits are recognized and sized to meet the target specifications. Simple model for distributed interconnect delays, is introduced and verified by Cadence simulations, their necessity is demonstrated. The models for the delay of a SRAM are used to determine the array sizes for a SRAM. An analytical delay model is proposed to predict the block size for SRAM; proposed model is based on dynamic strategies for word line charging and bit line discharging. Novel Sense Amplifier (SA) circuit for 2kb SRAM is presented and analyzed in this work. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of the current controlled SA. Butterfly architecture that is central decoding scheme is used to make a 2kb block from 1kb, after simulations, the maximum operating frequency of the system was found to be 800MHz

Investigating Input Offset Reduction with Timing Manipulation in Low Voltage Sense Amplifiers

Static Random Access Memories (SRAMs) are ubiquitous in modern computer systems. They provide a fast and relatively compact method of data storage. SRAM cells are read from and written to using analog differential bitline signals, BL and BLB. To increase operating speed and conserve power during a read cycle, cell access time is limited to a short duration. Since SRAM are often implemented with near-minimum sized devices to maximize memory density, the devices are relatively weak and can only generate a limited differential voltage during this read window, typically between 10mV to 100mV. Standard logic devices cannot read this small signal, so sense amplifiers are used to rapidly amplify it to logic levels. A key metric for a sense amplifier’s performance is its input-referred offset voltage, . This dictates the minimum required input voltage to produce a correct decision. A lower means that a shorter read window for the SRAM is required, and the overall read cycle can be performed at a higher frequency. Unfortunately, with the trends of technology scaling, the effects of device mismatches from process variation are becoming more significant. In sense amplifiers, this device mismatch will create a statistical spread of with a mean and standard deviation of and . To guarantee error-free operation, a lower bound for input differential voltage is set by the worst-case scenario from this spread. Another difficulty introduced with modern trends is low voltage operation. The drive strengths of devices in lower VDD systems are weaker, so any imbalances due to threshold mismatch can become more significant compared to the nominal quantities. This thesis explores methods of reducing input offset voltage of low voltage SRAM sense amplifiers with a primary goal of reducing . A circuit called the Delayed PMOS VLSA, or DVLSA, is proposed. The DVLSA is based on the common VLSA and uses a timing manipulation technique with its control signals. The circuit design attempts to reduce by reducing the mismatch contribution of the PMOS pull-up pair. The circuit is tested at 0.4V with the VLSA used as a reference. Statistical simulations show that for the PMOS pull-up pair varying in isolation, the circuit works as intended and is reduced. When all differential devices are varied, the DVLSA has a larger . Investigating the source of the failure using the isolated variation of the other two device pairs shows that the timing manipulation technique has a negative impact on the NMOS pair. It also suggests that the use of the DLVSA architecture introduces additional covariances when all differential devices are varied

Design of High Performance SRAM Based Memory Chip

The semiconductor memory SRAM uses bi-stable latch circuit to store the logic data 1 or 0. It differs from Dynamic RAM (DRAM) which needs periodic refreshment operation for the storage of logic data. Depending upon the frequency of operation SRAM power consumption varies i.e. it consumes very high power at higher frequencies like DRAM. The Cache memory present in the microprocessor needs high speed memory hence SRAM can be used for that purpose in microprocessors. The DRAM is normally used in the Main memory of processors, where importance is given to the density than its speed. The SRAM is also used in industrial subsystems, scientific and automotive electronics. In this thesis 16-Kb Memory is designed by using memory banking method in UMC 90nm technology ,which operates at a frequency of 1GHz.The post layout simulation for the complete design is performed and also obtained power analysis for the overall design. All peripherals like pre-charge, Row Decoder, Word line driver, Sense amplifier, Column Decoder/Mux and write driver are designed and layouts of all the above peripherals also drawn in an optimised manner such that their layout occupies minimum area. The 6T SRAM cell is designed with operating frequency of 8 GHz and stability analysis are also performed for single SRAM cell. The layout of Single SRAM cell is drawn in a symmetric manner, such that two adjacent cells can share same contact, which results reduction in the area of cell layout. The Static Noise Margin, Read noise margin and Write Noise Margin of single cell are found to be 240mV, 115mV and 425mV respectively for a supply voltage of 1V.The effect of pull-up ratio and cell ratio on the stability of SRAM cell is observed

Study and development of low power consumption SRAMs on 28 nm FD-SOI CMOS process

Since analog circuit designs in CMOS nanometer (< 90 nm) nodes can be substantially affected by manufacturing process variations, circuit performance becomes more challenging to achieve efficient solutions by using analytical models. Extensive simulations are thus commonly required to provide a high yield. On the other hand, due to the fact that the classical bulk MOS structure is reaching scaling limits (< 32 nm), alternative approaches are being developed as successors, such as fully depleted silicon-oninsulator (FD-SOI), Multigate MOSFET, FinFETs, among others, and new design techniques emerge by taking advantage of the improved features of these devices. This thesis focused on the development of analytical expressions for the major performance parameters of the SRAM cache implemented in 28 nm FD-SOI CMOS, mainly to explore the transistor dimensions at low computational cost, thereby producing efficient designs in terms of energy consumption, speed and yield. By taking advantage of both low computational cost and close agreement results of the developed models, in this thesis we were able to propose a non-traditional sizing procedure for the simple 6T-SRAM cell, that unlike the traditional thin-cell design, transistor lengths are used as a design variable in order to reduce the static leakage. The single-P-well (SPW) structure in combination with reverse-body-biasing (RBB) technique were used to achieve a better balance between P-type and N-type transistors. As a result, we developed a 128 kB SRAM cache, whose post-layout simulations show that the circuit consumes an average energy per operation of 0.604 pJ/word-access (64 I/O bits) at supply voltage of 0.45 V and operation frequency of 40 MHz. The total chip area of the 128 kB SRAM cache is 0.060 mm2 .O projeto de circuitos analogicos em processos nanométricos CMOS ( < 90 nm) per substancialmente afetado pelas variacões do processo de fabricacão, sendo cada vez mais desafiador para os projetistas alcançar soluções eficientes no desempenho dos circuitos mediante o uso de modelos analíticos. Simulacões extensas com alto custo com- putacional sao normalmente requeridas para providenciar um correto funcionamento do circuito. Por outro lado, devido ao fato que a estrutura bulk-CMOS esta alcançando seus limites de escala (< 32 nm), outros transistores foram desenvolvidos como sucessores, tais como o fully depleted silicon-on-insulator (FD-SOI), Multigate MOSFET, entre outros, surgindo novas tecnicas de projeto que utilizam as características aprimoradas destes dispositivos. Dessa forma, esta tese de doutorado se foca no desenvolvimento de modelos analíticos dos parametros mais importantes do cache SRAM implementado em processo CMOS FD-SOI de 28 nm, principalmente para explorar as dimensõoes dos transistores com baixo custo computacional, e assim produzir solucões eficientes em termos de consumo de energia, velocidade e rendimento. Aproveitando o baixo custo computacional e a alta concordância dos modelos analíticos, nesta tese fomos capazes de propor um dimensionamento nao tradicional para a célula de memória 6T-SRAM, em que diferentemente é do classico dimensionamento "thin-cell”, os comprimentos dos transistores são utilizados como variável de projeto com o fim de reduzir o consumo estático de corrente. A estrutura single-P-well (SPW), combinada com a técnica reverse-body-biasing (RBB) foram utilizadas para alcançar um melhor balanço entre as correntes específicas dos transistores do tipo P e N

Integrating simultaneous bi-direction signalling in the test fabric of 3D stacked integrated circuits.

Jennions, Ian K. - Associate SupervisorThe world has seen significant advancements in electronic devices’ capabilities, most notably the ability to embed ultra-large-scale functionalities in lightweight, area and power-efficient devices. There has been an enormous push towards quality and reliability in consumer electronics that have become an indispensable part of human life. Consequently, the tests conducted on these devices at the final stages before these are shipped out to the customers have a very high significance in the research community. However, researchers have always struggled to find a balance between the test time (hence the test cost) and the test overheads; unfortunately, these two are inversely proportional. On the other hand, the ever-increasing demand for more powerful and compact devices is now facing a new challenge. Historically, with the advancements in manufacturing technology, electronic devices witnessed miniaturizing at an exponential pace, as predicted by Moore’s law. However, further geometric or effective 2D scaling seems complicated due to performance and power concerns with smaller technology nodes. One promising way forward is by forming 3D Stacked Integrated Circuits (SICs), in which the individual dies are stacked vertically and interconnected using Through Silicon Vias (TSVs) before being packaged as a single chip. This allows more functionality to be embedded with a reduced footprint and addresses another critical problem being observed in 2D designs: increasingly long interconnects and latency issues. However, as more and more functionality is embedded into a small area, it becomes increasingly challenging to access the internal states (to observe or control) after the device is fabricated, which is essential for testing. This access is restricted by the limited number of Chip Terminals (IC pins and the vertical Through Silicon Vias) that a chip could be fitted with, the power consumption concerns, and the chip area overheads that could be allocated for testing. This research investigates Simultaneous Bi-Directional Signaling (SBS) for use in Test Access Mechanism (TAM) designs in 3D SICs. SBS enables chip terminals to simultaneously send and receive test vectors on a single Chip Terminal (CT), effectively doubling the per-pin efficiency, which could be translated into additional test channels for test time reduction or Chip Terminal reduction for resource efficiency. The research shows that SBS-based test access methods have significant potential in reducing test times and/or test resources compared to traditional approaches, thereby opening up new avenues towards cost-effectiveness and reliability of future electronics.PhD in Manufacturin