Current–Mode Fractional–Order Electronically Controllable Integrator Design

This contribution presents a design of a current–mode fractional–order electronically controllable integrator which can be used as a building block for a design of fractional–order (FO) circuits. The design is based on a 2nd–order Follow–the–Leader–Feedback topology which is suitably approximated to operate as an integrator of a fractional order. The topology is based on Operational Transconductance Amplifiers (OTAs), Adjustable Current Amplifiers (ACAs) and Current Follower (CF). The proposed structure offers the ability of the electronic control of its fractional order and also the electronic control of the frequency band. Simulations in Cadence IC6 (spectre) and more importantly experimental measurements were carried out to support the proposal. If wider bandwidth where the approximation is valid is required, a higher order structure must be used as also shown in this paper by utilization of a 4th–order FLF topology

Analogue Implementation of a Fractional-Order PI^{\lambda} Controller for DC Motor Speed Control

In this paper, an approach to design a fractional-order integral operator s(lambda) where -1 < lambda <0, using an analogue technique, is presented. The integrator with a constant phase angle -80.1 degree (i.e. order lambda = -0.89), bandwidth greater than 3 decades, and maximum relative phase error 1.38% is designed by cascade connection of first-order bilinear transfer segments and first-order low-pass filter. The performance of suggested realization is demonstrated in a fractional-order proportional-integral (FOPI lambda) controller described with proportional constant 1.37 and integration constant 2.28. The design specification corresponds to a speed control system of an armature controlled DC motor, which is often used in mechatronic and other fields of control theory. The behavior of both proposed analogue circuits employing two-stage Op-Amps is confirmed by SPICE simulations using TSMC 0.18 mu m level-7 LA) EN SCN018 CMOS process parameters with +/- 0.9 V supply voltages

Analog Implementation of Fractional-Order Elements and Their Applications

With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical “integer” methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems

A Novel Pseudo-Differential Integer/Fractional-Order Voltage-Mode All-Pass Filter

The paper presents the first- (integer) and fractional-order case studies of a novel pseudo-differential (P-D) voltage-mode all-pass filter (APF) employing a single differential voltage current conveyor (DVCC), one resistor, and a single grounded capacitor. The proposed filter brings significant reduction of complexity in comparison to available fully-differential or P-D filter topologies. Moreover, it was also shown that fractional-order capacitor can be used for gain response compensation of the proposed APF. The theoretical results of 0.8th and 1st-order APF were verified by Cadence IC6 Spectre simulations using new structure of DVCC via TSMC 0.18 µm CMOS process parameters supplied with ±0.9 V voltages

On the Design of Power Law Filters and Their Inverse Counterparts

This paper presents the optimal modeling of Power Law Filters (PLFs) with the low-pass (LP), high-pass (HP), band-pass (BP), and band-stop (BS) responses by means of rational approximants. The optimization is performed for three different objective functions and second-order filter mother functions. The formulated design constraints help avoid placement of the zeros and poles on the right-half s-plane, thus, yielding stable PLF and inverse PLF (IPLF) models. The performances of the approximants exhibiting the fractional-step magnitude and phase responses are evaluated using various statistical indices. At the cost of higher computational complexity, the proposed approach achieved improved accuracy with guaranteed stability when compared to the published literature. The four types of optimal PLFs and IPLFs with an exponent alpha of 0.5 are implemented using the follow-the-leader feedback topology employing AD844AN current feedback operational amplifiers. The experimental results demonstrate that the Total Harmonic Distortion achieved for all the practical PLF and IPLF circuits was equal or lower than 0.21%, whereas the Spurious-Free Dynamic Range also exceeded 57.23 and 54.72 dBc, respectively