Additive companding implementation to reduce ADC constraints for multiple signals digitization

International audienceIn urban sensor networks, the diversity of propagation conditions can lead to the simultaneous reception of signals having very different power levels. Given the diversity of wireless technologies used in this area, implementing gateways using a Software-Defined Radio (SDR) approach seems to be a very practical solution. Overcoming the large dynamic range may however require a very high resolution Analog-to-Digital Converter (ADC) to digitize the weakest signal with a satisfying precision. One possibility to relax this requirement is to use a companding technique before digitization. This paper describes how to use an additive companding approach to reduce ADC's complexity and proposes two implementations of the compressing law

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Design and distortion analysis of fully integrated image reject RF CMOS frontends

This thesis presents the design and experimental results of a 7.3GHz notch image reject filter, combined with a 5.8GHz low-noise amplifier (LNA), for integrated heterodyne receiver front-ends. A new image reject filter implementation is proposed. Q-enhancement circuitry for on-chip inductors are used to optimize the depth of image rejection. Experimental results show that more than 62dB of image rejection at 7.3GHz can be obtained in a standard CMOS 0.18mum technology, while operating from a 1.8V supply. The LNA exhibits a gain of 15.8dB and an IIP3 of -5.3dBm while consuming 9mW of power. With maximum image rejection, the LNA-notch combination circuit achieves a 4.1dB noise figure at 5.8GHz. The proposed notch filter alone can operate from a 1V supply voltage. It is shown analytically how circuit stability can be ensured.The implementation of new robust and stable high-Q CMOS image reject filters, which enables the realization of fully integrated heterodyne 5GHz RF receivers is also presented. A cascade of two notch filters with their image reject frequencies slightly offsetted is proposed, in order to obtain a wide image rejection bandwidth, without having to resort to the overhead of automatic tuning circuitry. Thus, power consumption, area, and complexity are significantly reduced. Experimental results show that more than 30d$ of image rejection can be obtained in a standard 0.18mum CMOS technology, over a 400MHz bandwidth centered at 7.4GHz

Nonlinear Distortion in Wideband Radio Receivers and Analog-to-Digital Converters: Modeling and Digital Suppression

Emerging wireless communications systems aim to flexible and efficient usage of radio spectrum in order to increase data rates. The ultimate goal in this field is a cognitive radio. It employs spectrum sensing in order to locate spatially and temporally vacant spectrum chunks that can be used for communications. In order to achieve that, flexible and reconfigurable transceivers are needed. A software-defined radio can provide these features by having a highly-integrated wideband transceiver with minimum analog components and mostly relying on digital signal processing. This is also desired from size, cost, and power consumption point of view. However, several challenges arise, from which dynamic range is one of the most important. This is especially true on receiver side where several signals can be received simultaneously through a single receiver chain. In extreme cases the weakest signal can be almost 100 dB weaker than the strongest one. Due to the limited dynamic range of the receiver, the strongest signals may cause nonlinear distortion which deteriorates spectrum sensing capabilities and also reception of the weakest signals. The nonlinearities are stemming from the analog receiver components and also from analog-to-digital converters (ADCs). This is a performance bottleneck in many wideband communications and also radar receivers. The dynamic range challenges are already encountered in current devices, such as in wideband multi-operator receiver scenarios in mobile networks, and the challenges will have even more essential role in the future.This thesis focuses on aforementioned receiver scenarios and contributes to modeling and digital suppression of nonlinear distortion. A behavioral model for direct-conversion receiver nonlinearities is derived and it jointly takes into account RF, mixer, and baseband nonlinearities together with I/Q imbalance. The model is then exploited in suppression of receiver nonlinearities. The considered method is based on adaptive digital post-processing and does not require any analog hardware modification. It is able to extract all the necessary information directly from the received waveform in order to suppress the nonlinear distortion caused by the strongest blocker signals inside the reception band.In addition, the nonlinearities of ADCs are considered. Even if the dynamic range of the analog receiver components is not limiting the performance, ADCs may cause considerable amount of nonlinear distortion. It can originate, e.g., from undeliberate variations of quantization levels. Furthermore, the received waveform may exceed the nominal voltage range of the ADC due to signal power variations. This causes unintentional signal clipping which creates severe nonlinear distortion. In this thesis, a Fourier series based model is derived for the signal clipping caused by ADCs. Furthermore, four different methods are considered for suppressing ADC nonlinearities, especially unintentional signal clipping. The methods exploit polynomial modeling, interpolation, or symbol decisions for suppressing the distortion. The common factor is that all the methods are based on digital post-processing and are able to continuously adapt to variations in the received waveform and in the receiver itself. This is a very important aspect in wideband receivers, especially in cognitive radios, when the flexibility and state-of-the-art performance is required

Companding Baseband Switched Capacitor Filters and ADCs for WLAN Applications

In this paper, system level design techniques for companding baseband switched capacitor (SC) filters for WLAN applications are presented. With companding, no AGC is required in front of the filter. A filter prototype is designed for 802.11g receiver and simulation results show that, with careful design of the opamps, a total harmonic distortion of less than 0.5% can be achieved. A new type of companding ADCs along with the algorithm to achieve companding in ADCs is proposed. It is shown that companding by a factor of 4 reduces the power consumption of the SC filter by a factor close to 4 times for a given dynamic range whereas it directly results In 12 dB reduction in the dynamic range requirement of the following ADC. © 2007 IEEE