34,681 research outputs found
Secure, performance-oriented data management for nanoCMOS electronics
The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is focused upon delivering a production level e-Infrastructure to meet the challenges facing the semiconductor industry in dealing with the next generation of âatomic-scaleâ transistor devices. This scale means that previous assumptions on the uniformity of transistor devices in electronics circuit and systems design are no longer valid, and the industry as a whole must deal with variability throughout the design process. Infrastructures to tackle this problem must provide seamless access to very large HPC resources for computationally expensive simulation of statistic ensembles of microscopically varying physical devices, and manage the many hundreds of thousands of files and meta-data associated with these simulations. A key challenge in undertaking this is in protecting the intellectual property associated with the data, simulations and design process as a whole. In this paper we present the nanoCMOS infrastructure and outline an evaluation undertaken on the Storage Resource Broker (SRB) and the Andrew File System (AFS) considering in particular the extent that they meet the performance and security requirements of the nanoCMOS domain. We also describe how metadata management is supported and linked to simulations and results in a scalable and secure manner
Compact Structural Test Generation for Analog Macros
A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IV-converter macro design. Parameters of so-called test configurations are optimized for detection of faults in a fault-list and an optimal selection algorithm results in determining the best test set. The distribution of the results along the parameter-axes of the test configurations is investigated to identify a collapsed high-quality test se
High Quality Compact Delay Test Generation
Delay testing is used to detect timing defects and ensure that a circuit meets its
timing specifications. The growing need for delay testing is a result of the advances in
deep submicron (DSM) semiconductor technology and the increase in clock frequency.
Small delay defects that previously were benign now produce delay faults, due to
reduced timing margins. This research focuses on the development of new test methods
for small delay defects, within the limits of affordable test generation cost and pattern
count.
First, a new dynamic compaction algorithm has been proposed to generate
compacted test sets for K longest paths per gate (KLPG) in combinational circuits or
scan-based sequential circuits. This algorithm uses a greedy approach to compact paths
with non-conflicting necessary assignments together during test generation. Second, to
make this dynamic compaction approach practical for industrial use, a recursive learning
algorithm has been implemented to identify more necessary assignments for each path,
so that the path-to-test-pattern matching using necessary assignments is more accurate.
Third, a realistic low cost fault coverage metric targeting both global and local delay
faults has been developed. The metric suggests the test strategy of generating a different
number of longest paths for each line in the circuit while maintaining high fault coverage.
The number of paths and type of test depends on the timing slack of the paths under this
metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits
show that the pattern count of KLPG can be significantly reduced using the proposed
methods. The pattern count is comparable to that of transition fault test, while achieving
higher test quality. Finally, the proposed ATPG methodology has been applied to an
industrial quad-core microprocessor. FMAX testing has been done on many devices and
silicon data has shown the benefit of KLPG test
Automated Netlist Generation for 3D Electrothermal and Electromagnetic Field Problems
We present a method for the automatic generation of netlists describing
general three-dimensional electrothermal and electromagnetic field problems.
Using a pair of structured orthogonal grids as spatial discretisation, a
one-to-one correspondence between grid objects and circuit elements is obtained
by employing the finite integration technique. The resulting circuit can then
be solved with any standard available circuit simulator, alleviating the need
for the implementation of a custom time integrator. Additionally, the approach
straightforwardly allows for field-circuit coupling simulations by
appropriately stamping the circuit description of lumped devices. As the
computational domain in wave propagation problems must be finite, stamps
representing absorbing boundary conditions are developed as well.
Representative numerical examples are used to validate the approach. The
results obtained by circuit simulation on the generated netlists are compared
with appropriate reference solutions.Comment: This is a pre-print of an article published in the Journal of
Computational Electronics. The final authenticated version is available
online at: https://dx.doi.org/10.1007/s10825-019-01368-6. All numerical
results can be reproduced by the Matlab code openly available at
https://github.com/tc88/ANTHE
Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition
A neuromorphic chip that combines CMOS analog spiking neurons and memristive
synapses offers a promising solution to brain-inspired computing, as it can
provide massive neural network parallelism and density. Previous hybrid analog
CMOS-memristor approaches required extensive CMOS circuitry for training, and
thus eliminated most of the density advantages gained by the adoption of
memristor synapses. Further, they used different waveforms for pre and
post-synaptic spikes that added undesirable circuit overhead. Here we describe
a hardware architecture that can feature a large number of memristor synapses
to learn real-world patterns. We present a versatile CMOS neuron that combines
integrate-and-fire behavior, drives passive memristors and implements
competitive learning in a compact circuit module, and enables in-situ
plasticity in the memristor synapses. We demonstrate handwritten-digits
recognition using the proposed architecture using transistor-level circuit
simulations. As the described neuromorphic architecture is homogeneous, it
realizes a fundamental building block for large-scale energy-efficient
brain-inspired silicon chips that could lead to next-generation cognitive
computing.Comment: This is a preprint of an article accepted for publication in IEEE
Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no.
2, June 201
Neutral conductor current in three-phase networks with compact fluorescent lamps
In this paper, expressions of the neutral conductor current in three-phase networks with compact fluorescent lamps (CFLs) are obtained from a CFL âblack-boxâ model proposed in the literature. These expressions allow studying and performing a sensitivity analysis of the impact of CFLs on neutral current. The influence of CFL model parameters, as well as supply voltage unbalance, number of CFLs per phase and different types of CFLs per phase, on the neutral current is also investigated. The obtained results are validated with measurements and PSCAD/EMTDC simulationsPeer ReviewedPreprin
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