Exact Synthesis for Logic Synthesis Applications with Complex Constraints

Exact synthesis is the problem of finding logic networks that represent given Boolean functions and respect given constraints. With exact synthesis it is possible to find optimum networks, e.g., in size or depth; consequently, it primarily finds application in logic optimization. However, exact synthesis is also very helpful in logic synthesis applications necessitating complex constraints that are present in the hardware primitives or the logic representations for which the synthesis has to be performed. Conventional heuristic logic synthesis algorithms are not considering such constraints. They still can be employed to optimize networks, but they cannot guarantee that optimized networks meets all requirements. Being faced with a logic synthesis application that seeks for low-depth majority-based networks with limited fan-out for small functions, we demonstrate how state-of-the-art exact synthesis algorithms can be adapted and used to find logic networks that match these constraints. To emphasize the need for exact synthesis, we also demonstrate how conventional logic synthesis either fails to find constraint-satisfying logic networks or yields networks of inferior quality

Functional Decomposition Using Majority

Typical operators for the decomposition of Boolean functions in state-of-the-art algorithms are AND, exclusive-OR (XOR), and a 2-to-1 multiplexer (MUX). We propose a logic decomposition algorithm that uses the majority-of-three (MAJ) operation. Such decomposition can extend the capabilities of current logic decomposition, but only found limited attention in previous work. Our algorithm makes use of a decomposition rule based on MAJ. Combined with disjoint-support decomposition, the algorithm can factorize XOR-Majority Graphs (XMGs), a recently proposed data structure which has XOR, MAJ, and inverters as only logic primitives. XMGs have been applied in various applications, including (i) exact synthesis aware rewriting, (ii) pre-optimization for 6-LUT mapping, and (iii) synthesis of quantum networks. An experimental evaluation shows that our algorithm leads to better XMGs compared to state-of-the-art algorithms, which positively affect all these three applications. As one example, our experiments show that the proposed method achieves up to 37.1% with an average of 9.6% reduction on the look-up tables (LUT) size/depth product applied to the EPFL arithmetic benchmarks after technology mapping

Classifying Functions with Exact Synthesis

Due to recent advances, constraint solvers have become efficient tools for synthesizing optimum Boolean circuits. We take advantage of this by showing how SAT based exact synthesis may be used as a method for finding minimum length Boolean chains. As opposed to other exact synthesis methods, ours may be easily parallelized, which we use to obtain a speedup of approximately 48 times. By combining our method with NPN canonization, we find for the first time the minimum length chains for all 4- and 5-input functions in terms of 3-input Boolean operators. Finally, we propose a hardware acceleration method for NPN canonization. It can be used to speed up NPN canonization in existing algorithms, and we believe it will allow us to find all 6-input NPN classes as well