The effect of an optical network on-chip on the performance of chip multiprocessors

Optical networks on-chip (ONoC) have been proposed to reduce power consumption and increase bandwidth density in high performance chip multiprocessors (CMP), compared to electrical NoCs. However, as buffering in an ONoC is not viable, the end-to-end message path needs to be acquired in advance during which the message is buffered at the network ingress. This waiting latency is therefore a combination of path setup latency and contention and forms a significant part of the total message latency. Many proposed ONoCs, such as Single Writer, Multiple Reader (SWMR), avoid path setup latency at the expense of increased optical components. In contrast, this thesis investigates a simple circuit-switched ONoC with lower component count where nodes need to request a channel before transmission. To hide the path setup latency, a coherence-based message predictor is proposed, to setup circuits before message arrival. Firstly, the effect of latency and bandwidth on application performance is thoroughly investigated using full-system simulations of shared memory CMPs. It is shown that the latency of an ideal NoC affects the CMP performance more than the NoC bandwidth. Increasing the number of wavelengths per channel decreases the serialisation latency and improves the performance of both ONoC types. With 2 or more wavelengths modulating at 25 Gbit=s , the ONoCs will outperform a conventional electrical mesh (maximal speedup of 20%). The SWMR ONoC outperforms the circuit-switched ONoC. Next coherence-based prediction techniques are proposed to reduce the waiting latency. The ideal coherence-based predictor reduces the waiting latency by 42%. A more streamlined predictor (smaller than a L1 cache) reduces the waiting latency by 31%. Without prediction, the message latency in the circuit-switched ONoC is 11% larger than in the SWMR ONoC. Applying the realistic predictor reverses this: the message latency in the SWMR ONoC is now 18% larger than the predictive circuitswitched ONoC

Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs

Design of an RSFQ Control Circuit to Observe MQC on an rf-SQUID

We believe that the best chance to observe macroscopic quantum coherence (MQC) in a rf-SQUID qubit is to use on-chip RSFQ digital circuits for preparing, evolving and reading out the qubit's quantum state. This approach allows experiments to be conducted on a very short time scale (sub-nanosecond) without the use of large bandwidth control lines that would couple environmental degrees of freedom to the qubit thus contributing to its decoherence. In this paper we present our design of a RSFQ digital control circuit for demonstrating MQC in a rf-SQUID. We assess some of the key practical issues in the circuit design including the achievement of the necessary flux bias stability. We present an "active" isolation structure to be used to increase coherence times. The structure decouples the SQUID from external degrees of freedom, and then couples it to the output measurement circuitry when required, all under the active control of RSFQ circuits. Research supported in part by ARO grant # DAAG55-98-1-0367.Comment: 4 pages. More information and publications at http://www.ece.rochester.edu:8080/users/sde/research/publications/index.htm

Physical implementations of quantum absorption refrigerators

Absorption refrigerators are autonomous thermal machines that harness the spontaneous flow of heat from a hot bath into the environment in order to perform cooling. Here we discuss quantum realizations of absorption refrigerators in two different settings: namely, cavity and circuit quantum electrodynamics. We first provide a unified description of these machines in terms of the concept of virtual temperature. Next, we describe the two different physical setups in detail and compare their properties and performance. We conclude with an outlook on future work and open questions in this field of research.Comment: Patrick P. Potts was formerly known as Patrick P. Hofe

All Optical Cellular Quantum Computer having Ancilla Bits for Operations in Each Cell

A quantum cellular network with a qubit and ancilla bits in each cell is proposed. The whole circuit works only with the help of external optical pulse sequences. In the operation, some of the ancilla bits are activated, and autonomous single- and two-qubit operations are made. In the sleep mode of a cell, the decoherence of the qubit is negligibly small. Since only two cells at most are active at once, the coherence can be maintained for a sufficiently long time for practical purposes. A device structure using a quantum dot array with possible operation and measurement schemes is also proposed.Comment: 14 pages, 5 figures RevTeX ;a single sentense is modified for the clarit

Quantum state engineering with Josephson-junction devices

We review recent theoretical and experimental progress in quantum state engineering with Josephson junction devices. The concepts of quantum computing have stimulated an increased activity in the field. Either charges or phases (fluxes) of the Josephson systems can be used as quantum degrees of freedom, and their quantum state can be manipulated coherently by voltage and current pulses. They thus can serve as qubits, and quantum logic gates can be performed. Their phase coherence time, which is limited, e.g., by the electromagnetic fluctuations in the control circuit, is long enough to allow a series of these manipulations. The quantum measurement process performed by a single-electron transistor, a SQUID, or further nanoelectronic devices is analyzed in detail.Comment: An article prepared for Reviews of Modern Physics, 46 pages, 23 figure