Fundamental study of underfill void formation in flip chip assembly

Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer pitch area array interconnects structured FCIP can be achieved using no-flow underfill assembly process. Using the assembly process, a high, stable yield assembly process recently reported with eutectic lead-tin solder interconnections, 150 µm pitch, and I/O counts in excess of 3000. The assembly process reported created a large number of voids among solder interconnects in FCIP. The voids formed among solder interconnections can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Moreover, these voids can severely reduce reliability performance. Indeed, many studies were conducted to examine the void formation in FCIP. Based on the studies, flip chip geometric design, process conditions, and material formulation have been considered as the potential causes of void formation. However, the present research won't be able to identify the mechanism of void formation, causing a lot of voids in assembly process without consideration of chemical reaction in the assembly process with a fine-pitch, high I/O density FCIP. Therefore, this research will present process technology necessary to achieve high yields in FCIP assemblies using no-flow underfills and investigate the underlying problem of underfill void formation in these assemblies. The plausible causes of void formation will be investigated using experimental techniques. The techniques will identify the primary source of the void formation. Besides, theoretical models will be established to predict the number of voids and to explain the growth behavior of voids in the FCIP. The established theoretical models will be verified by experiments. These models will validate with respect to the relationship between process parameters to achieve a high yield and to minimize voids in FCIP assemblies using no-flow underfill materials regarding process as well as material stand points. Eventually, this research provides design guideline achieving a high, stable yield and void-free assembly process.Ph.D.Committee Chair: Baldwin, Daniel; Committee Member: Colton, Jonathan; Committee Member: Ghiaasiaan, Mostafa; Committee Member: Moon, Jack; Committee Member: Tummala, Ra

Integrated Measurement Technique To Measure Curing Process-dependent Mechanical And Thermal Properties Of Polymeric Materials Using Fiber Bragg Grating Sensors

An innovative technique based on a fiber Bragg grating (FBG) sensor is proposed to measure the critical mechanical and thermal properties of polymeric materials. The properties include (1) chemical shrinkage evolution during curing, (2) modulus evolution during curing, (3) glass transition temperature (4) coefficient of thermal expansion (CTE), and (5) visco-elastic properties. Optimum specimen configurations are proposed from the theoretical analysis. Then an efficient numerical procedure is established to determine the material properties from the measured Bragg wavelength (BW) shift. The technique is implemented with various polymeric materials. The measured quantities are verified through a self-consistency test as well as the existing testing methods such as a warpage measurement of a bi-material strip, and a TMA measurement. The evolution properties obtained at a curing temperature are extended further by combining them with the conventional isothermal DSC experiments. Based on the existing theories, the evolution properties can be predicted at any temperatures. The proposed technique greatly enhances the capability to characterize the mechanical properties and behavior of polymeric materials. Since the specimen preparation is very straightforward, the proposed method can be routinely practiced and the measurement can be completely automated. It will provide a much-needed tool for rapid but accurate assessment of polymer properties, which, in turn, will enhance the accuracy of predictive modeling for design optimization of a microelectronics product at the conceptual stage of product development

Moisture and Interfacial Adhesion in Microelectronic Assemblies

In this research, a systematic and multi-disciplinary study was conducted to understand the fundamental science of moisture-induced degradation of interfacial adhesion. The research is comprised of both experimental and modeling components of analysis and consists of four primary components. First, the moisture transport behavior within underfill adhesives is experimentally characterized and incorporated into a finite element model to depict the moisture ingress and interfacial moisture concentration for each respective level of moisture preconditioning. Second, the effect of moisture on the variation of the underfill elastic modulus is demonstrated and the physical mechanisms for the change identified. Third, the aggregate effect of moisture on the interfacial fracture toughness of underfill to both copper and FR-4 board substrates is determined. This includes the primary effect of moisture being physically present at the interface and the secondary effect of moisture changing the elastic modulus of the adhesive when absorbed. Last, the recovery of both the elastic modulus and interfacial fracture toughness from moisture preconditioning is assessed with reversible and irreversible components identified. Using adsorption theory in conjunction with fracture mechanics, an analytical model is developed that predicts the loss in interfacial fracture toughness as a function of moisture content. The model incorporates key parameters relevant to the problem of moisture in epoxy joints identified from the experimental portion of this research, including the interfacial hydrophobicity, epoxy nanopore density, saturation concentration, and density of water. This research results in a comprehensive understanding of the primary mechanisms responsible for the interfacial degradation due to the presence of moisture. The experimental results obtained through this research provide definitive data for the electronics industry to use in their product design, failure analysis, and reliability modeling. The predictive model developed in this research provides a useful tool for developing new adhesives, innovative surface treatment methods, and effective protection methodologies for enhancing interfacial adhesion.Ph.D.Committee Chair: Jianmin Qu; Committee Member: C. P. Wong; Committee Member: S. Mostafa Ghiaasiaan; Committee Member: Suresh K. Sitaraman; Committee Member: W. Steven Johnso

The mechanics of network polymers with thermally reversible linkages.

Abstract Not Provide

Reliability testing and stress measurement of QFN packages encapsulated by an open-ended microwave curing system

In this paper, the influence of microwave curing on the reliability of a representative electronic package is examined by reliability testing and measurement of residual stresses. A LM358 voltage regulator die was mounted to an open Quad Flat No-leads package (QFN) for reliability testing. For the stress measurement, a specifically designed stress measurement die was mounted to the QFN package. The chips were encapsulated with Hysol EO1080 thermosetting polymer material. Curing was performed using an open-ended microwave oven system equipped with in situ temperature control. Three different temperature profiles for microwave curing were selected according to the requested degree of cure and chemical composition of the cured material. A convection cure profile was selected for the control group samples. Thermal cycling and HAST tests were performed on a total number of 80 chips. 95 QFN packages with stress measurement chips were also manufactured. Increased lifetime expectancy of the microwave cured packaged chips was experimentally demonstrated and measured between 62% to 149% increased lifetime expectancy after Temperature Cycling Test (TCT), and between 63% and 331% after highly Accelerated Ageing Test (HAST) and TCT compared to conventionally cured packages. Analysis of specifically designed stress test chips showed significantly lower residual stresses ranging from 26 MPa to 58.3 MPa within the microwave cured packages compared to conventionally cured packaged chips which displayed residual stresses ranging from 54 MPa to 80.5 MPa. This article therefore provides additional confidence in the industrial relevance of the microwave curing system and its advantages compared to traditional convection oven systems

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Peripheral soldering of flip chip joints on passive RFID tags

Flip chip is the main component of a RFID tag. It is used in billions each year in electronic packaging industries because of its small size, high performance and reliability as well as low cost. They are used in microprocessors, cell phones, watches and automobiles. RFID tags are applied to or incorporated into a product, animal, or person for identification and tracking using radio waves. Some tags can be read from several meters away or even beyond the line of sight of the reader. Passive RFID tags are the most common type in use that employ external power source to transmit signals. Joining chips by laser beam welding have wide advantages over other methods of joining, but they are seen limited to transparent substrates. However, connecting solder bumps with anisotropic conductive adhesives (ACA) produces majority of the joints. A high percentage of them fail in couple of months, particularly when exposed to vibration. In the present work, failure of RFID tags under dynamic loading or vibration was studied; as it was identified as one of the key issue to explore. Earlier investigators focused more on joining chip to the bump, but less on its assembly, i.e., attaching to the substrate. Either of the joints, between chip and bump or between antenna and bump can fail. However, the latter is more vulnerable to failure. Antenna is attached to substrate, relatively fixed when subjected to oscillation. It is the flip chip not the antenna moves during vibration. So, the joint with antenna suffers higher stresses. In addition to this, the strength of the bonding agent i.e., ACA also much smaller compared to the metallic bond at the other end of the bump. Natural frequency of RFID tags was calculated both analytically and numerically, found to be in kilohertz range, high enough to cause resonance. Experimental investigations were also carried out to determine the same. However, the test results for frequency were seen to be in hundred hertz range, common to some applications. It was recognized that the adhesive material, commonly used for joining chips, was primarily accountable for their failures. Since components to which the RFID tags are attached to experience low frequency vibration, chip joints fail as they face resonance during oscillation. Adhesives having much lower modulus than metals are used for attaching bumps to the substrate antennas, and thus mostly responsible for this reduction in natural frequency. Poor adhesive bonding strength at the interface and possible rise in temperature were attributed to failures under vibration. In order to overcome the early failure of RFID tag joints, Peripheral Soldering, an alternative chip joining method was devised. Peripheral Soldering would replace the traditional adhesive joining by bonding the peripheral surface of the bump to the substrate antenna. Instead of joining solder bump directly to the antenna, holes are to be drilled through antenna and substrate. S-bond material, a less familiar but more compatible with aluminum and copper, would be poured in liquid form through the holes on the chip pad. However, substrates compatible to high temperature are to be used; otherwise temperature control would be necessary to avoid damage to substrate. This S-bond would form metallic joints between chip and antenna. Having higher strength and better adhesion property, S-bond material provides better bonding capability. The strength of a chip joined by Peripheral Soldering was determined by analytical, numerical and experimental studies. Strength results were then compared to those of ACA. For a pad size of 60 micron on a 0.5 mm square chip, the new chip joints with Sbond provide an average strength of 0.233N analytically. Numerical results using finite element analysis in ANSYS 11.0 were about 1% less than the closed form solutions. Whereas, ACA connected joints show the maximum strength of 0.113N analytically and 0.1N numerically. Both the estimates indicate Peripheral Soldering is more than twice stronger than adhesive joints. Experimental investigation was carried out to find the strength attained with S-bond by joining similar surfaces as those of chip pad and antenna, but in larger scale due to limitation in facilities. Results obtained were moderated to incorporate the effect of size. Findings authenticate earlier predictions of superior strengths with S-bond. A comparison with ACA strength, extracted from previous investigations, further indicates that S-bond joints are more than 10 times stronger. Having higher bonding strength than in ACA joints, Peripheral Soldering would provide better reliability of the chip connections, i.e., RFID tags. The benefits attained would pay off complexities involved in tweaking

All-copper chip-to-substrate interconnects for high performance integrated circuit devices

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.Ph.D.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, Jame

Developing Metrology for Nondestructive Characterization of Buried Polymer Interfaces in Situ.

Polymers are widely used in modern microelectronics as adhesives, organic substrates, chip passivation layers, insulating dielectric materials, and photoresists in microlithography. The interfacial structures of polymer materials determine the interfacial properties of the materials. Weak adhesion or delamination at interfaces involving polymer materials can lead to failure of microelectronic devices. Therefore, it is important to investigate the molecular structures of such interfaces. However, it is difficult to study molecular structures of buried interfaces due to a lack of appropriate analytical techniques. This dissertation presents the development of the nonlinear optical technique sum frequency generation (SFG) vibrational spectroscopy into a metrology tool for nondestructive characterization of molecular structures at buried polymer interfaces in microelectronic packages in situ and the elucidation of relationships between buried molecular structures and interfacial properties such as adhesion strength. Buried polymer/epoxy, copper/epoxy, and silicon/organosilicate dielectric interfaces were investigated. SFG was used to directly probe molecular structures at buried adhesive interface in situ. Plasma treatment of polymer surfaces was found to alter the molecular structure at corresponding buried interfaces prepared using the plasma treated surfaces. Hygrothermal aging treatment was found to influence hydrophobic polymer/polymer interfaces less than hydrophilic interfaces, showing that hydrophobic materials can better resist delamination during qualification testing in high humidity environments. Copper/epoxy interfaces were found to delaminate near, but not exactly at, the metal/polymer interface and silane adhesion promoters were found to modify the interfacial region near the copper surface which suggests that the interfacial layer near copper needs to be modified to improve adhesion. Quantitative data analysis methodology was developed to simultaneously characterize the surface and buried interface of silicon-supported thin low-k polymer films nondestructively before and after microelectronic processing steps which provided a molecular level understanding of the effects of the processing. The general nature of the methodology enables it to be directly utilized to elucidate structure-property relationships at buried interfaces by correlating interfacial structures to interfacial properties. Structure-property relationships elucidated using this methodology can be used to guide the rational engineering of buried polymer interfaces with optimized properties in many practical applications such as polymer composites, optical fibers, paints, and anticorrosion coatings.PhDChemistryUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133179/1/myersjn_1.pd

Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.M.S.Committee Chair: Rao R. Tummala; Committee Member: C. P. Wong; Committee Member: P. M. Ra