4 research outputs found
Enabling Intra-Plane Parallel Block Erase to Alleviate the Impact of Garbage Collection
Garbage collection (GC) in NAND flash can significantly decrease I/O performance in SSDs by
copying valid data to other locations, thus blocking incoming I/O requests. To help improve
performance, NAND flash utilizes various advanced commands to increase internal parallelism.
Currently, these commands only parallelize operations across channels, chips, dies, and planes,
neglecting the block-level and below due structural bottlenecks along the data path and risk of
disturbances that can compromise valid data by inducing errors. However, due to the triple-well
structure of the NAND flash plane architecture and erasing procedure, it is possible to erase
multiple blocks within a plane, in parallel, without being restricted by structural limitations or
diminishing the integrity of the valid data. The number of page movements due to multiple block
erases can be restrained so as to bound the overhead per GC. Moreover, more capacity can be
reclaimed per GC which delays future GCs and effectively reduces their frequency. Such an
Intra-Plane Parallel Block Erase (IPPBE) in turn diminishes the impact of GC on incoming
requests, improving their response times. Experimental results show that IPPBE can reduce the
time spent performing GC by up to 50.7% and 33.6% on average, read/write response time by up
to 47.0%/45.4% and 16.5%/14.8% on average respectively, page movements by up to 52.2% and
26.6% on average, and blocks erased by up to 14.2% and 3.6% on average. An energy analysis
conducted indicates that by reducing the number of page copies and the number of block erases,
the energy cost of garbage collection can be reduced up to 44.1% and 19.3% on average
Flash Memory Devices
Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement