Evaluation and Suppression Method of Turn-off Current Spike for SiC/Si Hybrid Switch

SiC MOSFET/Si IGBT (SiC/Si) hybrid switch usually selects the gate control pattern that SiC MOSFET turns on earlier and turns off later than Si IGBT, with the aim of making the hybrid switch show excellent switching characteristics of SiC MOSFET and reduce switching loss. However, when SiC MOSFET turns off, the fast slew rate of drain source voltage causes the current spike in Si IGBT due to the effects of parasitic capacitance charging and carrier recombination, which will produce additional turn-off loss, thus affecting the overall efficiency and temperature rise of the converter. Based on the double pulse test circuit of SiC/Si hybrid switch, the mathematical model of the turn-off transient process is established. The effects of the remnant carrier recombination degree of Si IGBT, the turn-off speed of SiC MOSFET and the working conditions on the turn-off current spike of hybrid switch are evaluated. Although adjusting these parameters can reduce the turn-off current spike somewhat, additional losses will be introduced. Therefore, a new method to suppress the turn-off current spike is proposed to balance the power loss and current stress

Efficiency Analysis of Drive-train for an Electrified Vehicle

In this PhD thesis, various solutions to improve the energy efficiency in the electrical drive-train of an electrified vehicle such as modifications of the propulsion inverter or control of the electric machine, are proposed and their benefits are quantified from an energy efficiency point of view. The efficiency analysis is based on modeling of a power electronics inverter, an electric machine and a battery in various drive cycles for an electrified vehicle.</br> Several solutions are studied for the propulsion inverter. It is shown that by replacing a Silicon pn freewheeling diode in the propulsion inverter with a Silicon Carbide (SiC) diode, an average of up to 1.5 % improvement in the drive cycle efficiency can be expected. Furthermore, by replacing the Silicon IGBTs in the inverter with SiC MOSFETs, the drive cycle efficiency in NEDC can be increased between 2 to 5 percent.</br> Several solutions to improve the efficiency in a PMSM (Permanent Magnet Synchronous Machine) are investigated. An improved MTPA (Maximum Torque per Ampere) is implemented accounting for the variable nature of the machine parameters due to saturation and temperature. Moreover, the iron losses are accounted for in the derivations of an appropriate maximum torque per ampere angle. It is shown that the low-speed and standstill torque characteristics of a selected PMSM with high current density can be improved by 7 % when using a proposed MTPA algorithm instead of an ordinary MTPA algorithm where the equivalent circuit parameters of the PMSM are updated online outside the optimization algorithm. Furthermore, the efficiency can also be improved up to 5 % at the low-speed and high-torque operating region. However, the overall energy efficiency improvement for a certain drive cycle is not significant and can be up to 0.2 %.</br> Finally a controllable dc-link voltage for the propulsion inverter is investigated in order to quantify the energy efficiency gain for the inverter and the motor. Their drive cycle energy efficiency improvement is up to one percent when using a SiC based inverter and up to 4 percent for an IGBT based inverter

Design Considerations for Paralleling Multiple Chips in SiC Power Modules

With the benefits of fast switching speed, low on-resistance and high thermal conductivity, silicon carbide (SiC) devices are being implemented in converter designs with high efficiency and high power density. Consequently, SiC power modules are needed. However, some of the preestablished package designs for silicon based power modules are not suitable to manifest the advantages of SiC devices. Therefore, this thesis aims at optimizing the package design to utilize the fast switching capability of SiC devices. First, the power loop parasitic inductance induced by the package can lead to large voltage spikes with the fast switching SiC device. It can potentially exceed the device’s voltage ratings and affect its safe operation. Second, to achieve high power density design with SiC devices, the package’s cooling performance needs to be improved. Third, to design a package for high current applications with multiple chips in parallel, a proper scaling method is needed to ensure all the devices undertake the same voltage stress in switching transients. For P-cell/N-cell designs with split scaling, a new parasitic parameter, namely, middle-point parasitic inductance Lmiddle will be introduced. Its role should be understood. Lastly, the unbalanced dynamic switching loss can lead to different state junction temperatures among paralleled devices. Thermal coupling can help to reduce the temperature imbalance, and its role should be quantitatively investigated. To meet the first two requirements, a new package design is proposed with reduced parasitic inductance and double-sided cooling. Compared to a baseline package, more than 60% reduction of parasitic inductance is achieved. The middle-point parasitic inductance’s effect on device’s switching transients is analyzed in the frequency domain. Then a dedicated power module is fabricated with the capability of varying Lmiddle. Experiment results show that as Lmiddle increases, different voltage stresses are imposed on the MOSFET and anti-parallel diode. Electrothermal simulations are implemented to investigate steady state junction temperatures of paralleled devices considering unbalanced switching losses at different thermal coupling conditions. It is observed that both devices’ junction temperatures will increase as the coupling coefficient is increased. However, the junction temperature imbalance will decrease. This is verified by the experiment result

Characterization and Modeling of Silicon Carbide Power Devices and Paralleling Operation”,

Abstract-This paper presents recent research on several silicon carbide (SiC) power devices. The devices have been tested for both static and dynamic characteristics, which show the advantages over their Si counterparts. The temperature dependency of these characteristics has also been presented in this paper. Then, simulation work of paralleling operation of SiC power MOSFETs based on a verified device model in Pspice is presented to show the impact of parasitics in the circuit on the switching performance

Performance and robustness characterisation of SiC power MOSFETs

Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics

Performance and robustness characterisation of SiC power MOSFETs

Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics

Characterization Methodology, Modeling, and Converter Design for 600 V Enhancement-Mode GaN FETs

Gallium Nitride (GaN) power devices are an emerging technology that have only become available commercially in the past few years. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This dissertation reviews the unique characteristics, commercial status, and design challenges that surround GaN FETs, in order to provide sufficient background to potential GaN-based converter designers.Methodology for experimentally characterizing a GaN FET was also presented, including static characterization with a curve tracer and impedance analyzer, as well as dynamic characterization in a double pulse test setup. This methodology was supplemented by additional tests to determine losses caused by Miller-induced cross talk, and the tradeoff between these losses and overlap losses was studied for one example device.Based on analysis of characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The impact of the Miller effect during the turn-on transient was studied, as well as the dynamic performance of GaN at elevated temperature.Furthermore, solutions were proposed for several key design challenges in GaN-based converters. First, a driver-integrated overcurrent and short-circuit protection scheme was developed, based on the relationship between gate voltage and drain current in GaN gate injection transistors. Second, the limitations on maximum utilization of current and voltage in a GaN FET were studied, particularly the voltage overshoots following turn-on and turn-off switching transients, and the effective cooling of GaN FETs in higher power operation. A thermal design was developed for heat extraction from bottom-cooled surface-mount devices. These solutions were verified in a GaN-based full-bridge single-phase inverter