A Low Noise Variable Gain Amplifier with 97.2 dB Linear Gain Range for CW Radar

This manuscript reports the design of a low noise variable gain amplifier (VGA) having wide dB linear gain characteristics for a continuous wave (CW) radar. A pseudo-exponential gain control function has been adopted in this VGA for the wide dB-linear behavior. Also, a BJT-based gain stage has been proposed to improve the gain dynamic range and low noise performance due to its higher transconductance/gain and lower flicker noise contribution. This proposed 2-gain stage VGA has been implemented in 130 nm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) technology. This design performance has been benchmarked by post-layout simulation results. It has demonstrated a voltage-controlled gain from -33.6 dB to 74.4 dB (total 108 dB), with a 97.2 dB linear gain range, input referred noise of 2.4 nV /√Hz, and power consumption of 4.25 mW. This VGA has a 3-dB bandwidth of 10 MHz at a maximum gain of 74.4 dB and 251 MHz at a minimum gain of -33.6 dB with a chip layout area of 0.0682 mm2 . Compared to the latest available CMOS/BiCMOS VGAs in the literature, this proposed VGA has the highest gain dynamic range and dB-linear gain range with minimum input referred noise simultaneously across the operation bandwidth

Cell-based variable-gain amplifiers with accurate dB-linear characteristic in 0.18 µm CMOS technology

A simple and robust “cell-based” method is presented for the design of variable-gain amplifiers (VGAs). The proposed unit cell utilizes a unique gain compensation method and achieves accurate dB-linear characteristic across a wide tuning range with low power consumption and wide bandwidth. Several such highly dB-linear unit cells can be cascaded to provide the required gain range for a VGA. To prove the concept, single-cell, 5-cell, 10-cell and 15-cell reconfigurable VGAs were fabricated in a standard 0.18 μm CMOS technology. The measurement results show that the 10-cell VGA achieves a gain range of 38.6 dB with less than 0.19 dB gain error. The 15-cell VGA can either be used as reconfigurable VGA for analog control voltage or tunable PGA for digital control stream, with the flexibility of scaling gain range, gain error/step and power consumption. For the VGA at highest gain setting, it consumes 1.12 mW and achieves a gain range of 56 dB, gain error less than 0.3 dB.Accepted versio

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity