An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Modélisation comportementale d'un réseau sur puce basé sur des interconnexions RF.

The development of multiprocessor systems integrated on chip (MPSoC) respondsto the growing need for intensive computation systems. However, the evolutionof their performances is hampered by their communication networks on chip(NoC) due to their energy consumption and delay. It is in this context that the wired RF network on chip (RFNoC) was emerged. In order to better manage and optimize the design of an RFNoC, it is necessary to develop a simulation platform adressing both analog and digital circuits.First, a time domaine simulation of an RFNoC with components whose modelsare ideal is used to optimize the allocation of the available spectrum resources. Where appropriate, we provide solutions to improve the quality of transmitted signal. Secondly, we have developed, in VHDL-AMS, behavioral and accurate models of all RFNoC components. The models of the low noise amplifier (LNA) and the mixer take into account the parameters for the amplification, nonlinearities, noise and bandwidth. The model of the local oscillator considers the conventional parameters, including its phase noise. Concerning the transmission line, an accurate frequency model, including the skin effect is adapted for time domaine simulations. Then, the impact of component parameters on RFNoC performances is evaluatedto anticipate constraints of the RFNoC design.Le développement des systèmes multiprocesseurs intégrés sur puce (MPSoC) répond au besoin grandissant des architectures de calcul intensif. En revanche, l'évolution de leurs performances est entravée par leurs réseaux de communication sur puce (NoC) à cause de leur consommation d'énergie ainsi que du retard. C'est dans ce contexte que les NoC à base d'interconnexions RF et filaires (RFNoC) ont émergé. Afin de gérer au mieux et d'optimiser la conception d'un RFNoC, il est indispensable de développer une plateforme de simulation intégrant à la fois des circuits analogiques et numériques.Dans un premier temps, la simulation temporelle d'un RFNoC avec des composants dont les modèles sont idéaux est utilisée pour optimiser l'allocation des ressources spectrales disponibles. Le cas échéant, nous proposons des solutions pour améliorer la qualité de signal transmis. Dans un deuxième temps, nous avons développé en VHDL-AMS des modèles comportementaux et précis de chacun des composants du RFNoC. Les modèles de l'amplificateur faible bruit (LNA) et du mélangeur, prennent en compte les paramètres concernant, l'amplification, les non-linéarités, le bruit et la bande passante. Le modèle de l'oscillateur local considère les paramètresconventionnels, notamment le bruit de phase. Quant à la ligne de transmission, un modèle fréquentiel précis, incluant l'effet de peau est adapté pour les simulations temporelles. Ensuite, l'impact des paramètres des composants sur les performances du RFNoC est évalué afin d'anticiper les contraintes qui s'imposeront lors de la conception du RFNoC