Built-in self-test and self-calibration for analog and mixed signal circuits

Analog-to-digital converters (ADC) are one of the most important components in modern electronic systems. In the mission-critical applications such as automotive, the reliability of the ADC is critical as the ADC impacts the system level performance. Due to the aging effect and environmental changes, the performance of the ADC may degrade and even fail to meet the accuracy requirement over time. Built-in self-test (BIST) and self-calibration are becoming the ultimate solution to achieve lifetime reliability. This dissertation introduces two ADC testing algorithms and two ADC built-in self-test circuit implementations to test the ADC integral nonlinearity (INL) and differential nonlinearity (DNL) on-chip. In the first testing algorithm, the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) is developed for ADC built-in self-test, which eliminates the need for precision stimulus and reduces the overall test time. In this algorithm, the ADC is tested twice with a nonlinear ramp, instead of using a linear ramp signal. Therefore, the stimulus can be easily generated on-chip in a low-cost way. For the two ramps, there is a constant voltage shift in between. As the input stimulus linearity is completely relaxed, there is no requirement on the waveform of the input stimulus as long as it covers the ADC input range. In the meantime, the high-resolution ADC linearity is modeled with segmented parameters, which reduces the number of samples required for achieving high-precision test, thus saving the test time. As a result, the USER-SMILE algorithm is able to use less than 1 sample/code nonlinear stimulus to test high resolution ADCs with less than 0.5 least significant bit (LSB) INL estimation error, achieving more than 10-time test time reduction. This algorithm is validated with both board-level implementation and on-chip silicon implementation. The second testing algorithm is proposed to test the INL/DNL for multi-bit-per-stages pipelined ADCs with reduced test time and better test coverage. Due to the redundancy characteristics of multi-bit-per-stages pipelined ADC, the conventional histogram test cannot estimate and calibrate the static linearity accurately. The proposed method models the pipelined ADC nonlinearity as segmented parameters with inter-stage gain errors using the raw codes instead of the final output codes. During the test phase, a pure sine wave is sent to the ADC as the input and the model parameters are estimated from the output data with the system identification method. The modeled errors are then removed from the digital output codes during the calibration phase. A high-speed 12-bit pipelined ADC is tested and calibrated with the proposed method. With only 4000 samples, the 12-bit ADC is accurately tested and calibrated to achieve less than 1 LSB INL. The ADC effective number of bits (ENOB) is improved from 9.7 bits to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by more than 20dB after calibration. In the first circuit implementation, a low-cost on-chip built-in self-test solution is developed using an R2R digital-to-analog converter (DAC) structure as the signal generator and the voltage shift generator for ADC linearity test. The proposed DAC is a subradix-2 R2R DAC with a constant voltage shift generation capability. The subradix-2 architecture avoids positive voltage gaps caused by mismatches, which relaxes the DAC matching requirements and reduces the design area. The R2R DAC based BIST circuit is fabricated in TSMC 40nm technology with a small area of 0.02mm^2. Measurement results show that the BIST circuit is capable of testing a 15-bit ADC INL accurately with less than 0.5 LSB INL estimation error. In the second circuit implementation, a complete SAR ADC built-in self-test solution using the USER-SMILE is developed and implemented in a 28nm automotive microcontroller. A low-cost 12-bit resistive DAC with less than 12-bit linearity is used as the signal generator to test and calibrate a SAR ADC with a target linearity of 12 bits. The voltage shift generation is created inside the ADC with capacitor switching. The entire algorithm processing unit for USER-SMILE algorithm is also implemented on chip. The final testing results are saved in the memory for further digital calibration. Both the total harmonic distortion (THD) and the SFDR are improved by 20dB after calibration, achieving -84.5dB and 86.5dB respectively. More than 700 parts are tested to verify the robustness of the BIST solution

Background Calibration of a 6-Bit 1Gsps Split-Flash ADC

In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC\u27 calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed continuously in the background in the digital domain. The proposed flash ADC has an effective-number-of-bits (ENOB) of 6-bits and is designed for a target sampling rate of 1Gs/s in 180nm CMOS. The calibration algorithm described has been simulated in MATLAB and an FPGA implementation has been investigated

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Error Compensation in Pipeline and Converters

This thesis provides an improved calibration and compensation scheme for pipeline Analog-to-Digital Converters (ADCs). This new scheme utilizes the intermediate stage outputs in a pipeline to characterize error mechanisms in the architecture. The goal of this compensation scheme is to increase the dynamic range of the ADC. The pipeline architecture is described in general, and tailored to the 1.5 bitslstage topology. Dominant error mechanisms are defined and characterized for an arbitrary stage in the pipeline. These error mechanisms are modeled with basis functions. The traditional calibration scheme is modified and used to iteratively calculate the error characteristics. The information from calibration is used to compensate the ADC. The calibration and compensation scheme is demonstrated both in simulation and using a custom hardware pipeline ADC. A 10-bit 5 MHz ADC was designed and fabricated in 0.5 pm CMOS to serve as the demonstration platform. The scheme was successful in showing improvements in dynamic range while using intermediate stage outputs to efficiently model errors in a pipeline stage. An application of the technique on the real converter showed an average of 8.6 dB improvement in SFDR in the full Nyquist band of the ADC. The average improvement in SINAD and ENOB are 3.2 dB and 0.53 bits respectively

Bi-Linear Homogeneity Enforced Calibration for Pipelined ADCs

Pipelined analog-to-digital converters (ADCs) are key enablers in many state-of-the-art signal processing systems with high sampling rates. In addition to high sampling rates, such systems often demand a high linearity. To meet these challenging linearity requirements, ADC calibration techniques were heavily investigated throughout the past decades. One limitation in ADC calibration is the need for a precisely known test signal. In our previous work, we proposed the homogeneity enforced calibration (HEC) approach, which circumvents this need by consecutively feeding a test signal and a scaled version of it into the ADC. The calibration itself is performed using only the corresponding output samples, such that the test signal can remain unknown. On the downside, the HEC approach requires the option to accurately scale the test signal, impeding an on-chip implementation. In this work, we provide a thorough analysis of the HEC approach, including the effects of an inaccurately scaled test signal. Furthermore, the bi-linear homogeneity enforced calibration (BL-HEC) approach is introduced and suggested to account for an inaccurate scaling and, therefore, to facilitate an on-chip implementation. In addition, a comprehensive stability and convergence analysis of the BL-HEC approach is carried out. Finally, we verify our concept with simulations.Comment: 12 pages, 5 figure