End-of-fabrication CMOS process monitor

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's)

Development of a radiation-hard CMOS process

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth

Charged particle detection performances of CMOS pixel sensors produced in a 0.18 um process with a high resistivity epitaxial layer

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 um thin CMOS Pixel Sensors (CPS) covering either the 3 innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 um CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 um CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 10^13 n_eq/cm^2 was observed to yield a SNR ranging between 11 and 23 for coolant temperatures varying from 15 C to 30 C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation respectively. These satisfactory results allow to validate the TowerJazz 0.18 um CMOS process for the ALICE ITS upgrade.Comment: (v2) Added hyper-links; (v3) A typo correcte

On-chip timing measurement architecture with femtosecond resolution

A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185µm) in a 0.12µm CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date

A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previous designs (a few Gb/s), but at much lower power than recently published work. Both low static power and low dynamic power (low energy per bit) is aimed for. A capacitive pre-emphasis transmitter lowers the voltage swing and increases the bandwidth using a simple inverter based transceiver and capacitive coupling to the interconnect. The receiver uses Decision Feedback Equalization with a power-efficient continuous-time feedback filter. A low power latch-type voltage sense amplifier is used. The transceiver, fabricated in a 1.2V 90nm CMOS process, achieves 2Gb/s. It consumes only 0.28pJ/b, which is 7 times lower than earlier work

Active inductor shunt peaking in high-speed VCSEL driver design

An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all transistor active inductor shunt peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been tapped out, and the prototype has been proofed by the preliminary electrical test results and bit error ratio test results. The driver achieves 8-Gbps data rate as simulated with the peaking. We present the all transistor active inductor shunt peaking structure, simulation and test results in this paper.Comment: 4 pages, 6 figures and 1 table, Submitted to 'Chinese Physics C

CMOS Terahertz Metamaterial Based 64 × 64 Bolometric Detector Arrays

We present two terahertz detectors composed of microbolometer sensors (vanadium oxide and silicon pn diode) and metamaterial absorbers monolithically integrated into a complementary metal oxide semiconductor (CMOS) process. The metamaterial absorbers were created using the metal-dielectric-metal layers of a commercial CMOS technology resulting in low-cost terahertz detectors. The scalability of this technology was used to form a 64 × 64 pixel terahertz focal plane array

Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

A wideband noise-canceling CMOS LNA exploiting a transformer

A broadband LNA incorporating single-ended to differential conversion, has been successfully implemented using a noise-canceling technique and a single on-chip transformer. The LNA achieves a high voltage gain of 19dB, a wideband input match (2.5-4.0 GHz), and a noise figure of 4-5.4 dB, while consuming only 8mW. The LNA is implemented in a 90nm CMOS process with 6 metal layers