1,077 research outputs found
What constitutes a nanoswitch? A Perspective
Progress in the last two decades has effectively integrated spintronics and
nanomagnetics into a single field, creating a new class of spin-based devices
that are now being used both to Read (R) information from magnets and to Write
(W) information onto magnets. Many other new phenomena are being investigated
for nano-electronic memory as described in Part II of this book. It seems
natural to ask whether these advances in memory devices could also translate
into a new class of logic devices.
What makes logic devices different from memory is the need for one device to
drive another and this calls for gain, directionality and input-output
isolation as exemplified by the transistor. With this in mind we will try to
present our perspective on how W and R devices in general, spintronic or
otherwise, could be integrated into transistor-like switches that can be
interconnected to build complex circuits without external amplifiers or clocks.
We will argue that the most common switch used to implement digital logic based
on complementary metal oxide semiconductor (CMOS) transistors can be viewed as
an integrated W-R unit having an input-output asymmetry that give it gain and
directionality. Such a viewpoint is not intended to provide any insight into
the operation of CMOS switches, but rather as an aid to understanding how W and
R units based on spins and magnets can be combined to build transistor-like
switches. Next we will discuss the standard W and R units used for magnetic
memory devices and present one way to integrate them into a single unit with
the input electrically isolated from the output. But we argue that this
integrated W-R unit would not provide the key property of gain. We will then
show that the recently discovered giant spin Hall effect could be used to
construct a W-R unit with gain and suggest other possibilities for spin
switches with gain.Comment: 27 pages. To appear in Emerging Nanoelectronic Devices, Editors: An
Chen, James Hutchby, Victor Zhirnov and George Bourianoff, John Wiley & Sons
(to be published
Integrating nano-logic into an undergraduate logic design course
The goal of this work is to motivate our students and enhance their ability to address newer logic blocks namely majority gates in the existing framework. We use a K-map based methodology to introduce a few novel nano-logic design concepts for the undergraduate logic design class. We want them to possess knowledge about a few fundamental abstracted logical behaviors of future nano-devices and their functionality which in turn would motivate them to further investigate these non-CMOS emerging devices, logics and architectures. This would augment critical thinking of the students where they apply the learnt knowledge to a novel/unfamiliar situation. We intend to augment the existing standard EE and CS courses by inserting K-map based knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework. Experiments with our students show that all the students were able to grasp the basic concept of majority logic synthesis and almost 63 of them had a deeper understanding of the synthesis algorithm demonstrated to them
Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices
Protecting intellectual property (IP) in electronic circuits has become a
serious challenge in recent years. Logic locking/encryption and layout
camouflaging are two prominent techniques for IP protection. Most existing
approaches, however, particularly those focused on CMOS integration, incur
excessive design overheads resulting from their need for additional circuit
structures or device-level modifications. This work leverages the innate
polymorphism of an emerging spin-based device, called the giant spin-Hall
effect (GSHE) switch, to simultaneously enable locking and camouflaging within
a single instance. Using the GSHE switch, we propose a powerful primitive that
enables cloaking all the 16 Boolean functions possible for two inputs. We
conduct a comprehensive study using state-of-the-art Boolean satisfiability
(SAT) attacks to demonstrate the superior resilience of the proposed primitive
in comparison to several others in the literature. While we tailor the
primitive for deterministic computation, it can readily support stochastic
computation; we argue that stochastic behavior can break most, if not all,
existing SAT attacks. Finally, we discuss the resilience of the primitive
against various side-channel attacks as well as invasive monitoring at runtime,
which are arguably even more concerning threats than SAT attacks.Comment: Published in Proc. Design, Automation and Test in Europe (DATE) 201
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