1,032 research outputs found
Free Level Threshold Zone (FLTZ) Logic For Mixed Analog-Digital Closed Loop Circuitry [TK7887.6. N335 2008 f rb].
Para penyelidik sentiasa mencari cara-cara penambahbaikan kaedah antara muka antara domain Analog dan Digital.
Researchers have always look for ways to improve the interfacing method between the Analog and Digital domain
Theory and applications of delta-sigma analogue-to-digital converters without negative feedback
Analog-to-digital converters play a crucial role in modern audio and communication design. Conventional Nyquist converters are suitable only for medium resolutions and require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can achieve high resolutions (>20bits) and can be implemented using straightforward, high-tolerance analog components. In conventional oversampled modulators, negative feedback is applied in order to control the dynamic behavior of a system and to realize the attenuation of the quantization noise in the signal band due to noise shaping. However, feedback can also introduce undesirable effects such as limit cycles, jitter problems in continuous-time topologies, and infinite impulse responses. Additionally, it increases the system complexity due to extra circuit components such as nonlinear multi-bit digital-to-analog converters in the feedback path. Moreover, in certain applications such as wireless, biomedical sensory, or microphone implementations feedback cannot be applied. As a result, the main goal of this thesis is to develop sigma-delta data converters without feedback. Various new delta-sigma analog-to-digital converter topologies are explored their mathematical models are presented. Simulations are carried out to validate these models and to show performance results. Specifically, two topologies, a first-order and a second-order oscillator-based delta-sigma modulator without feedback are described in detail. They both can be implemented utilizing VCOs and standard digital gates, thus requiring only few components. As proof of concept, two digital microphones based on these delta-sigma converters without feedback were implemented and experimental results are given. These results show adequate performance and provide a new approach of measuring
Robust low power CMOS methodologies for ISFETs instrumentation
I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process
to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor
(ISFET) for pH detection. In circuit design, I have developed frequency domain signal
processing, which transforms pH information into a frequency modulated signal. The
frequency modulated signal is subsequently digitized and encoded into a bit-stream of data.
The architecture of the instrumentation system consists of a) A novel front-end averaging
amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high
linear voltage controlled oscillator for converting the voltage signal into a frequency
modulated signal, and c) Digital gates for digitizing and differentiating the frequency
modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st
order sigma delta modulation, whose noise floor is shaped by +20dB/decade.
The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip
responds linearly to the pH in a chemical solution and produces a digital output, with up to an
8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS
processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’
threshold voltages into atypical values. As compared to other ISFET-related works in the
literature, the instrumentation system proposed in this thesis can cope with the mismatched
ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very
accurate and robust for chemical sensing
Wireless electrode for electrocardiogram (ECG) signal.
by Leung Sze-wing.Thesis (M.Phil.)--Chinese University of Hong Kong, 1999.Includes bibliographical references (leaves 79-84).Abstracts in English and Chinese.ACKNOWLEDGEMENT --- p.IIABSTRACT --- p.III摘要 --- p.VCONTENTS --- p.VIChapter CHAPTER 1 --- INTRODUCTION --- p.1Chapter 1.1 --- Objectives --- p.1Chapter 1.2 --- Prevalence of Heart Diseases --- p.1Chapter 1.3 --- Importance of ECG Monitoring --- p.2Chapter 1.4 --- Wireless Electrode --- p.2Chapter 1.5 --- Analogue-to-Digital Converters --- p.3Chapter 1.6 --- Organization of Thesis --- p.4Chapter CHAPTER 2 --- LITERATURE REVIEW --- p.5Chapter 2.1 --- Telemetry --- p.5Chapter 2.1.1 --- "Definitions of ""Telemetry “" --- p.5Chapter 2.1.2 --- Advantages of Telemetry --- p.6Chapter 2.1.3 --- History of Telemetry --- p.7Chapter 2.1.4 --- Special Considerations on Telemetry System --- p.10Chapter 2.2 --- Sigma-Delta Converter --- p.12Chapter 2.2.1 --- Conventional Digitizing Circuitry --- p.12Chapter 2.2.2 --- "Single, Dual-Slope A/D Converters" --- p.13Single-Slope A/D Converter --- p.13Dual-Slope Converter --- p.75Chapter 2.2.3 --- Successive Approximation (SAR) --- p.17Chapter 2.2.4 --- Flash Converters --- p.18Chapter 2.2.5 --- Sigma-Delta Converter --- p.18Chapter 2.3 --- Conclusion --- p.20Chapter CHAPTER 3 --- WIRELESS ELECTRODE --- p.21Chapter 3.1 --- """Single Electrode"" Measurement" --- p.21Chapter 3.2 --- VSE (Virtual Single Electrode) --- p.21Concentric Electrode --- p.21Chapter 3.3 --- WE (Wireless Electrode) --- p.24Chapter 3.4 --- Discussion --- p.29Chapter CHAPTER 4 --- SIGMA-DELTA CONVERTER FOR ECG SIGNALS --- p.30Chapter 4.1 --- Motivations --- p.30Chapter 4.2 --- Baseband Application --- p.31Chapter 4.2.1 --- Simulation Results --- p.31Chapter 4.2.2 --- Experimental Results --- p.48Chapter 4.3 --- Wireless Application --- p.58Chapter 4.3.1 --- General Description --- p.58Chapter 4.3.2 --- Simulation Results --- p.59Chapter 4.3.3 --- Scenario 1 (Analogue Decoding) --- p.70Chapter 4.3.4 --- Scenario II (Digital Decoding) --- p.73Chapter 4.4 --- Discussion and Conclusion --- p.76Chapter CHAPTER 5 --- CONCLUSION AND FUTURE WORK --- p.77Chapter 5.1 --- General Conclus ion --- p.77Chapter 5.2 --- Future Work --- p.78BIBLIOGRAPHY --- p.79LIST OF ABBREVIATIONS --- p.8
Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology
Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning
applications has increased the demand of MEMS-based digital microphones.
Mobile devices have several microphones enabling noise canceling, acoustic beamforming
and speech recognition. With the development of machine learning applications
the interest to integrate sensors with neural networks has increased.
This has driven the interest to develop digital microphones in nanometer CMOS
nodes where the microphone analog-front end and digital processing, potentially
including neural networks, is integrated on the same chip.
Traditionally, analog-to-digital converters (ADCs) in digital microphones have
been implemented using high order Sigma-Delta modulators. The most common
technique to implement these high order Sigma-Selta modulators is switchedcapacitor
CMOS circuits. Recently, to reduce power consumption and make them
more suitable for tasks that require always-on operation, such as keyword recognition,
switched-capacitor circuits have been improved using inverter-based operational
amplifier integrators. Alternatively, switched-capacitor based Sigma-
Delta modulators have been replaced by continuous time Sigma-Delta converters.
Nevertheless, in both implementations the input signal is voltage encoded
across the modulator, making the integration in smaller CMOS nodes more challenging
due to the reduced voltage supply.
An alternative technique consists on encoding the input signal on time (or
frequency) instead of voltage. This is what time-encoded converters do. Lately,
time-encoding converters have gained popularity as they are more suitable to
nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have
drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs).
VCO-ADCs can be implemented using CMOS inverter based ring oscillators
(RO) and digital circuitry. They also show noise-shaping properties.
This makes them a very interesting alternative for implementation of ADCs in
nanometer CMOS nodes. Nevertheless, two main circuit impairments are present
in VCO-ADCs, and both come from the oscillator non-idealities. The first of them
is the oscillator phase noise, that reduces the resolution of the ADC. The second
is the non-linear tuning curve of the oscillator, that results in harmonic distortion
at medium to high input amplitudes.
In this thesis we analyze the use of time encoding ADCs for MEMS microphones
with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we
study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in
sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations
for the noise transfer function (NTF) of a third order sigma-delta using a second
order filter and the NSQ are presented.
Secondly, we move our attention to the topic of RO-ADCs. We present a high
dynamic range MEMS microphone 130nm CMOS chip based on an open-loop
VCO-ADC. This dissertation shows the implementation of the analog front-end
that includes the oscillator and the MEMS interface, with a focus on achieving
low power consumption with low noise and a high dynamic range. The digital
circuitry is left to be explained by the coauthor of the chip in his dissertation. The
chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5%
at 128 dBSPL with a power consumption of 438μW.
After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement
an unsampled feedback loop around the oscillator. The objective is to reduce
distortion. Additionally phase noise mitigation is achieved. A first topology
including an operational amplifier to increase the loop gain is analyzed. The design
is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR
with an analog power consumption of 600μW. A second topology without the
operational amplifier is also analyzed. Two chips are designed with this topology.
The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto-
digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a
power consumption of 482μW. The second chip includes only the oscillator and
is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog
power consumption is 153μW.
To finish this thesis, two circuits that use an FDR with a ring oscillator are
presented. The first is a capacity-to-digital converter (CDC). The second is a filter
made with an FDR and an oscillator intended for voice activity detection tasks
(VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de
machine-learning han aumentado la demanda de micrófonos digitales basados
en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación
de ruido, el beamforming o conformación de haces y el reconocimiento
de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés
por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el
interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde
el front-end analógico y el procesamiento digital del micrófono, que puede
incluir redes neuronales, está integrado en el mismo chip.
Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos
digitales han sido implementados utilizando moduladores Sigma-Delta de
orden elevado. La técnica más común para implementar estos moduladores Sigma-
Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente,
para reducir el consumo de potencia y hacerlos más adecuados para las tareas que
requieren una operación continua, como el reconocimiento de palabras clave, los
convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con
el uso de integradores implementados con amplificadores operacionales basados
en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas
han sido reemplazados por moduladores en tiempo continuo. No obstante,
en ambas implementaciones, la señal de entrada es codificada en voltaje durante
el proceso de conversión, lo que hace que la integración en nodos CMOS más
pequeños sea complicada debido a la menor tensión de alimentación.
Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o
frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación
temporal. Recientemente, los convertidores de codificación temporal
han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos
que los convertidores Sigma-Delta. Entre los que más interés han despertado
encontramos los ADCs basados en osciladores controlados por tensión
(VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo
(RO) implementados con inversores CMOS y circuitos digitales. Esta familia
de convertidores también tiene conformado de ruido. Esto los convierte en una
alternativa muy interesante para la implementación de convertidores en nodos
CMOS nanométricos. Sin embargo, dos problemas principales están presentes en
este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero
de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no
lineal del oscilador, lo que causa distorsión a amplitudes medias y altas.
En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos
MEMS, con especial interés en ADCS basados en osciladores de anillo
(RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado
de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador
agrega un orden adicional de conformado de ruido al modulador, mejorando la
resolución. En este documento se explica el cuantificador y obtienen las ecuaciones
para la función de transferencia de ruido (NTF) de un sigma-delta de tercer
orden usando un filtro de segundo orden y el NSQ.
En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos
el chip de un micrófono MEMS de alto rango dinámico en CMOS de
130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación
del front-end analógico que incluye el oscilador y la interfaz con
el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un
bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La
descripción del back-end digital se deja para la tesis del couator del chip. La
SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD
de 1,5% a 128 dBSPL y un consumo de potencia de 438μW.
Finalmente, se analiza el uso de una resistencia dependiente de frecuencia
(FDR) para implementar un bucle de realimentación no muestreado alrededor
del oscilador. El objetivo es reducir la distorsión. Además, también se logra la
mitigación del ruido de fase del oscilador. Se analyza una primera topologia de
realimentación incluyendo un amplificador operacional para incrementar la ganancia
de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que
logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la
parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador
operacional. Se fabrican y miden dos chips diseñados con esta topologia.
El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye
el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de
76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador
y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el
el consumo de potencia analógica es de 153μW.
Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador
en anillo. El primero es un convertidor de capacidad a digital (CDC). El
segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de
detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout
Comparison of Hysteresis Based PWM Schemes ΔΣ-PWM and Direct Torque Control
This paper presents the differences and similarities of ΔΣ-PWM as a hysteresis-based PWM scheme with direct torque control (DTC) using simulation models. The variable switching frequency caused by the hysteresis element is examined with regard to its instantaneous values. The comparison is based on an equal maximum switching frequency as a design criterion. With this first assumption, the variation of the instantaneous switching frequency is higher when using DTC because of the temporary prioritization of one inverter leg. Besides the lower variation, ΔΣ-PWM shows a higher average switching frequency. Because the switching frequency is related to the torque ripple, the usage of ΔΣ-PWM results in a smaller torque ripple. Due to the dependence of torque ripple on switching frequency, a second comparison is carried out based on the same average switching frequency. In this comparison the ΔΣ-PWM shows higher torque ripple than DTC
Study of voltage controlled oscillator based analog-to-digital converter
A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This thesis analyzes the performance of VCO-based ADCs in the presence of non idealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described.
Further, the study involves the use of VCO based Dual-slope A/D converter and its behaviour under different input voltage level. Graph is plotted between output voltages of the integrator vs. time. Digital circuits like a bit-counter and logic circuits are used for operation mode. A normal VCO model is also done in MATLAB-simulink environment and studied under variable input frequency and corresponding output plots are view
- …