Efficient algorithms for dilated mappings of binary trees

The problem is addressed to find a 1-1 mapping of the vertices of a binary tree onto those of a target binary tree such that the son of a node on the first binary tree is mapped onto a descendent of the image of that node in the second binary tree. There are two natural measures of the cost of this mapping, namely the dilation cost, i.e., the maximum distance in the target binary tree between the images of vertices that are adjacent in the original tree. The other measure, expansion cost, is defined as the number of extra nodes/edges to be added to the target binary tree in order to ensure a 1-1 mapping. An efficient algorithm to find a mapping of one binary tree onto another is described. It is shown that it is possible to minimize one cost of mapping at the expense of the other. This problem arises when designing pipelined arithmetic logic units (ALU) for special purpose computers. The pipeline is composed of ALU chips connected in the form of a binary tree. The operands to the pipeline can be supplied to the leaf nodes of the binary tree which then process and pass the results up to their parents. The final result is available at the root. As each new application may require a distinct nesting of operations, it is useful to be able to find a good mapping of a new binary tree over existing ALU tree. Another problem arises if every distinct required binary tree is known beforehand. Here it is useful to hardwire the pipeline in the form of a minimal supertree that contains all required binary trees

Asymptotic proportion of arbitrage points in fractional binary markets

A fractional binary market is an approximating sequence of binary models for the fractional Black-Scholes model, which Sottinen constructed by giving an analogue of the Donsker's theorem. In a binary market the arbitrage condition can be expressed as a condition on the nodes of a binary tree. We call "arbitrage points" the points in the binary tree which verify such an arbitrage condition and "arbitrage paths" the paths in the binary tree which cross at least one arbitrage point. Using this terminology, a binary market admits arbitrage if and only if there is at least one arbitrage point in the binary tree or equivalently if there is at least one arbitrage path. Following the lines of Sottinen, who showed that the arbitrage persists in the fractional binary market, we further prove that starting from any point in the tree, we can reach an arbitrage point. This implies that, in the limit, there is an infinite number of arbitrage points. Next, we provide an in-depth analysis of the asymptotic proportion of arbitrage points at asymptotic levels and of arbitrage paths in the fractional binary market. All these results are obtained by studying a rescaled disturbed random walk. We moreover show that, when $H$ is close to $1$, with probability $1$ a path in the binary tree crosses an infinite number of arbitrage points. In particular, for such $H$, the asymptotic proportion of arbitrage paths is equal to $1$

Topological self-similarity on the random binary-tree model

Asymptotic analysis on some statistical properties of the random binary-tree model is developed. We quantify a hierarchical structure of branching patterns based on the Horton-Strahler analysis. We introduce a transformation of a binary tree, and derive a recursive equation about branch orders. As an application of the analysis, topological self-similarity and its generalization is proved in an asymptotic sense. Also, some important examples are presented

High-Performance Architecture for Binary-Tree-Based Finite State Machines

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%