Memristor: Modeling, Simulation and Usage in Neuromorphic Computation

Memristor, the fourth passive circuit element, has attracted increased attention from various areas since the first real device was discovered in 2008. Its distinctive characteristic to record the historic profile of the voltage/current through itself creates great potential in future circuit design. Inspired by its high Scalability, ultra low power consumption and similar functionality to biology synapse, using memristor to build high density, high power efficiency neuromorphic circuits becomes one of most promising and also challenging applications. The challenges can be concluded into three levels: device level, circuit level and application level. At device level, we studied different memristor models and process variations, then we carried out three independent variation models to describe the variation and stochastic behavior of TiO2 memristors. These models can also extend to other memristor models. Meanwhile, these models are also compact enough for large-scale circuit simulation. At circuit level, inspired by the large-scale and unique requirement of memristor-based neuromorphic circuits, we designed a circuit simulator for efficient memristor cross-point array simulations. Out simulator is 4~5 orders of magnitude faster than tradition SPICE simulators. Both linear and nonlinear memristor cross-point arrays are studied for level-based and spike-based neuromorphic circuits, respectively. At application level, we first designed a few compact memristor-based neuromorphic components, including ``Macro cell'' for efficient and high definition weight storage, memristor-based stochastic neuron and memristor-based spatio temporal synapse. We then studied three typical neural network models and their hardware realization on memristor-based neuromorphic circuits: Brain-State-in-a-Box (BSB) model stands for level-based neural network, and STDP/ReSuMe models stand for spiking neural network for temporal learning. Our result demonstrates the high resilience to variation of memristor-based circuits and ultra-low power consumption. In this thesis, we have proposed a complete and detailed analysis for memristor-based neuromorphic circuit design from the device level to the application level. In each level, both theoretical analysis and experimental data versification are applied to ensure the completeness and accuracy of the work

A Software-equivalent SNN Hardware using RRAM-array for Asynchronous Real-time Learning

Spiking Neural Network (SNN) naturally inspires hardware implementation as it is based on biology. For learning, spike time dependent plasticity (STDP) may be implemented using an energy efficient waveform superposition on memristor based synapse. However, system level implementation has three challenges. First, a classic dilemma is that recognition requires current reading for short voltage$-$spikes which is disturbed by large voltage$-$waveforms that are simultaneously applied on the same memristor for real$-$time learning i.e. the simultaneous read$-$write dilemma. Second, the hardware needs to exactly replicate software implementation for easy adaptation of algorithm to hardware. Third, the devices used in hardware simulations must be realistic. In this paper, we present an approach to address the above concerns. First, the learning and recognition occurs in separate arrays simultaneously in real$-$time, asynchronously $-$ avoiding non$-$biomimetic clocking based complex signal management. Second, we show that the hardware emulates software at every stage by comparison of SPICE (circuit$-$simulator) with MATLAB (mathematical SNN algorithm implementation in software) implementations. As an example, the hardware shows 97.5 per cent accuracy in classification which is equivalent to software for a Fisher$-$Iris dataset. Third, the STDP is implemented using a model of synaptic device implemented using HfO2 memristor. We show that an increasingly realistic memristor model slightly reduces the hardware performance (85 per cent), which highlights the need to engineer RRAM characteristics specifically for SNN.Comment: Eight pages, ten figures and two table

A quantization-aware regularized learning method in multi-level memristor-based neuromorphic computing system

Neuromorphic computing, a VLSI realization of neuro-biological architecture, is inspired by the working mechanism of human-brain. As an example of a promising design methodology, synapse design can be greatly simplified by leveraging the similarity between the biological synaptic weight of a synapse and the programmable resistance (memristance) of a memristor. However, programming the memristors to the target values can be very challenging due to the impact of device variations and the limitation of the peripheral CMOS circuitry. A quantization process is used to map analog weights to discrete resistance states of the memristors, which introduces a quantization loss. In this thesis, we propose a regularized learning method that is able to take into account the deviation of the memristor-mapped synaptic weights from the target values determined during the training process. Experimental results obtained when utilizing the MNIST data set show that compared to the conventional learning method which considers the learning and mapping processes separately, our learning method can substantially improve the computation accuracy of the mapped two-layer multilayer perceptron (and LeNet-5) on multi-level memristor crossbars by 4.30% (11.05%) for binary representation, and by 0.40% (8.06%) for three-level representation

Neuromorphic System Design and Application

With the booming of large scale data related applications, cognitive systems that leverage modern data processing technologies, e.g., machine learning and data mining, are widely used in various industry fields. These application bring challenges to conventional computer systems on both semiconductor manufacturing and computing architecture. The invention of neuromorphic computing system (NCS) is inspired by the working mechanism of human-brain. It is a promising architecture to combat the well-known memory bottleneck in Von Neumann architecture. The recent breakthrough on memristor devices and crossbar structure made an important step toward realizing a low-power, small-footprint NCS on-a-chip. However, the currently low manufacturing reliability of nano-devices and circuit level constrains, .e.g., the voltage IR-drop along metal wires and analog signal noise from the peripheral circuits, bring challenges on scalability, precision and robustness of memristor crossbar based NCS. In this dissertation, we quantitatively analyzed the robustness of memristor crossbar based NCS when considering the device process variations, signal fluctuation and IR-drop. Based on our analysis, we will explore deep understanding on hardware training methods, e.g., on-device training and off-device training. Then, new technologies, e.g., noise-eliminating training, variation-aware training and adaptive mapping, specifically designed to improve the training quality on memristor crossbar hardware will be proposed in this dissertation. A digital initialization step for hardware training is also introduced to reduce training time. The circuit level constrains will also limit the scalability of a single memristor crossbar, which will decrease the efficiency of implementation of NCS. We also leverage system reduction/compression techniques to reduce the required crossbar size for certain applications. Besides, running machine learning algorithms on embedded systems bring new security concerns to the service providers and the users. In this dissertation, we will first explore the security concerns by using examples from real applications. These examples will demonstrate how attackers can access confidential user data, replicate a sensitive data processing model without any access to model details and how expose some key features of training data by using the service as a normal user. Based on our understanding of these security concerns, we will use unique property of memristor device to build a secured NCS

Enabling Neuromorphic Computing for Artificial Intelligence with Hardware-Software Co-Design

In the last decade, neuromorphic computing was rebirthed with the emergence of novel nano-devices and hardware-software co-design approaches. With the fast advancement in algorithms for today’s artificial intelligence (AI) applications, deep neural networks (DNNs) have become the mainstream technology. It has been a new research trend to enable neuromorphic designs for DNNs computing with high computing efficiency in speed and energy. In this chapter, we will summarize the recent advances in neuromorphic computing hardware and system designs with non-volatile resistive access memory (ReRAM) devices. More specifically, we will discuss the ReRAM-based neuromorphic computing hardware and system implementations, hardware-software co-design approaches for quantized and sparse DNNs, and architecture designs