BOOM - A Heuristic Boolean Minimizer

This paper presents an algorithm for two-level Boolean minimization (BOOM) based on a new implicant generation paradigm. In contrast to all previous minimization methods, where the implicants are generated bottom-up, the proposed method uses a top-down approach. Thus, instead of increasing the dimensionality of implicants by omitting literals from their terms, the dimension of a term is gradually decreased by adding new literals. The method is advantageous especially for functions with many input variables (up to thousands) and with only few care terms defined, where other minimization tools are not applicable because of the long runtime. The method has been tested on several different kinds of problems and the results were compared with ESPRESSO

Configurational Approach to Identify Concept Networks in selected Clinical Safety Incident Classes

Classifying clinical safety incidents (CSI) in their correct classes depends on the multiple concepts used to describe them. Machine learning based classification case study presented in this paper shows that it fails to identify the underlying complex concepts associations between the CSI classes. Two pairs of classes, each having high and low confused classes (as determined by the classifier), were further investigated by applying the set-theoretic-based logical synthesis methodology. The aim is to identify the relationships between concept networks for selected classes. The concept networks were identified using a set of 117 terms and measures taken included degree-centrality and in-betweenness centrality. In this study, using deterministic configurational approach, it is feasible to draw a meaningful relationship between concepts using the complex medical dataset sourced from the Incident Information Management System. The study is proof of concept that it is possible to identify concept networks and concept configuration rules for CSI classes

Minish HAT: A Tool for the Minimization of Here-and-There Logic Programs and Theories in Answer Set Programming

[Abstract] When it comes to the writing of a new logic program or theory, it is of great importance to obtain a concise and minimal representation, for simplicity and ease of interpretation reasons. There are already a few methods and many tools, such as Karnaugh Maps or the Quine-McCluskey method, as well as their numerous software implementations, that solve this minimization problem in Boolean logic. This is not the case for Here-and-There logic, also called three-valued logic. Even though there are theoretical minimization methods for logic theories and programs, there aren’t any published tools that are able to obtain a minimal equivalent logic program. In this paper we present the first version of a tool called that is able to efficiently obtain minimal and equivalent representations for any logic program in Here-and-There. The described tool uses an hybrid method both leveraging a modified version of the Quine-McCluskey algorithm and Answer Set Programming techniques to minimize fairly complex logic programs in a reduced time

Parity Codes Used for On-Line Testing in FPGA

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented.

Logic Synthesis as an Efficient Means of Minimal Model Discovery from Multivariable Medical Datasets

In this paper we review the application of logic synthesis methods for uncovering minimal structures in observational/medical datasets. Traditionally used in digital circuit design, logic synthesis has taken major strides in the past few decades and forms the foundation of some of the most powerful concepts in computer science and data mining. Here we provide a review of current state of research in application of logic synthesis methods for data analysis and provide a demonstrative example for systematic application and reasoning based on these methods

A Network-Based Deterministic Model for Causal Complexity

Despite the widespread use of techniques and tools for causal analysis, existing methodologies still fall short as they largely regard causal variables as independent elements, thereby failing to appreciate the significance of the interactions of causal variables. The prospect of inferring causal relationships from weaker structural assumptions compels for further research in this area. This study explores the effects of the interactions of variables in the context of causal analysis, and introduces new advancements to this area of research. In this study, we introduce a new approach for the causal complexity with the goal of making the solution set closer to deterministic by taking into consideration the underlying patterns embedded within a dataset; in particular, the interactions of causal variables. Our model follows the configurational approach, and as such, is able to account for the three major phenomena of conjunctural causation, equifinality, and causal asymmetry

On 3-share Threshold Implementations for 4-bit S-boxes

One of the most promising lightweight hardware countermeasures against SCA attacks is the so-called Threshold Implementation (TI) countermeasure. In this work we resolve many of the remaining open issues towards it\u27s applicability. In particular, our contribution is three-fold: first we define which optimal (from a cryptographic point of view) S-boxes can be implemented with a 3-share TI. Second, we introduce two methodologies to efficiently implement these S-boxes. Third, as an example, we successfully apply these methodologies to PRESENT and are able to decrease the area requirements of its protected S-box by 57\%

Pushing the Limits: Searching for Implementations with the Smallest Area for Lightweight S-Boxes

The area is one of the most important criteria for an S-box in hardware implementation when designing lightweight cryptography primitives. The area can be well estimated by the number of gate equivalent (GE). However, to our best knowledge, there is no efficient method to search for an S-box implementation with the least GE. Previous approaches can be classified into two categories, one is a heuristic that aims at finding an implementation with a satisfying but not necessarily the smallest GE number; the other one is SAT-based focusing on only the smallest number of gates while it ignored that the areas of different gates vary. Implementation with the least gates would usually not lead to the smallest number of GE. In this paper, we propose an improved SAT-based tool targeting optimizing the number of GE of an S-box implementation. Given an S-box, our tool can return the implementation of this S-box with the smallest number of GE. We speed up the search process of the tool by bit-sliced technique. Additionally, our tool supports 2-, 3-, and 4-input gates, while the previous tools cover only 2-input gates. To highlight the strength of our tool, we apply it to some 4-bit and 5-bit S-boxes of famous ciphers. We obtain a better implementation of RECTANGLE\u27s S-box with the area of 18.00GE. What\u27s more, we prove that the implementations of S-boxes of PICCOLO, SKINNY, and LBLOCK in the current literature have been optimal. When using the DC synthesizer on the circuits produced by our tool, the area are much better than the circuits converted by DC synthesizers from the lookup tables (LUT). At last, we use our tool to find implementations of 5-bit S-boxes, such as those used in KECCAK and ASCON