Remotely Managed Logic Built-In Self-Test for Secure M2M Communications

A rapid growth of Machine-to-Machine (M2M) communications is expected in the coming years. M2M applications create new challenges for in-field testing since they typically operate in environments where human supervision is difficult or impossible. In addition, M2M networks may be significant in size. We propose to automate Logic Built-In Self-Test (LBIST) by using a centralized test management system which can test all end-point M2M devices in the same network. Such a method makes possible transferring some of the LBIST functionality from the devices under test to the test management system. This is important for M2M devices which have very limited computing resources and commonly are battery-powered. In addition, the presented method provides protection against both random and malicious faults including some types of hardware Trojans

Modeling of design-for-test infrastructure in complex systems-on-chips

Every integrated circuit contains a piece of design-for-test (DFT) infra- structure in order to guarantee the chip quality after manufacture. The DFT resources are employed only once in the fab and are usually not available during regular system operation. In order to assess the hardware integrity of a chip over its complete life- cycle, it is promising to reuse the DFT infrastructure as part of system- level test. In this thesis, the provided system, a Tricore processor from Infineon, must be partitioned and modified in order to enable the autonomous structural test of every component of the system in the field without expensive external tester

Built-In Self Test (BIST) for Realistic Delay Defects

Testing of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models

BIST for Systems-On-A-Chip

An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPS, and many other functions, and built-in seltest is the appropriate method for testing complex systems composed of different cores