Low-level estimation at high-levels of abstraction in system-level design

Embedded systems are becoming increasingly complex with shortening time-tomarket demands. System-level modeling and design have been proposed to help embedded system development keep pace with this complexity. In a system-level design environment, a designer is able to delay critical design decisions until late in the design cycle, reducing the risk of making incorrect decisions which could require a costly redesign. New methods of estimating system-level performance must be devised to accommodate these needs.;In embedded systems composed of off-the-shelf parts, performance can be roughly estimated using part documentation. However, this process can provide poor estimates. Additionally, if the design includes a custom part, there may not be detailed documentation from which to gather performance estimates. The exhaustive gathering of estimates is error prone and tedious. In this thesis we present a novel estimation technique called minimal characterization for creating system-level estimation metrics. We show that estimates can be orders of magnitude more accurate, without any loss in fidelity, using a small number of source-level metrics. We show results from applying a source-level performance estimation technique generally used on software systems to a system-level design that is implemented in both software and hardware targets. Finally, we present a categorization of secondary execution factors which can greatly affect the accuracy of system-level estimates but have only been peripherally addressed in other approaches

Automatic application partitioning on FPGA/CPU systems based on detailed low-level information

Re configurable FPGA/CPU systems are widely described in literature as a viable processing solution for embedded and high end processing. One of the key issues of this kind of approach is the code partitioning between CPU and FPGA. The development of automatic partitioning tools allows to obtain optimized architecture without a specific knowledge of digital design. In this paper we present a framework which, starting from an ANSI C application code: (i) automatically identifies code fragments suitable for hardware implementation as specialized functional units (ii)for all these segments a synthesizable code is generated and sent to a synthesis tool, (iii) from the synthesis results, the segments to be implemented on FPGA are selected (iv) bitstream to configure the FPGA and modified C code to be executed on the CPU are generated. We applied this tool to standard benchmarks obtaining, with respect to state of the art, an improvement of up to 250% in the accuracy of performances estimation related to the selected segments of code. This leads to a more optimized code partitioning. \uc2\ua9 2006 IEEE