5 research outputs found
Low Complexity Belief Propagation Polar Code Decoders
Since its invention, polar code has received a lot of attention because of
its capacity-achieving performance and low encoding and decoding complexity.
Successive cancellation decoding (SCD) and belief propagation decoding (BPD)
are two of the most popular approaches for decoding polar codes. SCD is able to
achieve good error-correcting performance and is less computationally expensive
as compared to BPD. However SCDs suffer from long latency and low throughput
due to the serial nature of the successive cancellation algorithm. BPD is
parallel in nature and hence is more attractive for high throughput
applications. However since it is iterative in nature, the required latency and
energy dissipation increases linearly with the number of iterations. In this
work, we borrow the idea of SCD and propose a novel scheme based on
sub-factor-graph freezing to reduce the average number of computations as well
as the average number of iterations required by BPD, which directly translates
into lower latency and energy dissipation. Simulation results show that the
proposed scheme has no performance degradation and achieves significant
reduction in computation complexity over the existing methods.Comment: 6 page
A High-Throughput Energy-Efficient Implementation of Successive-Cancellation Decoder for Polar Codes Using Combinational Logic
This paper proposes a high-throughput energy-efficient Successive
Cancellation (SC) decoder architecture for polar codes based on combinational
logic. The proposed combinational architecture operates at relatively low clock
frequencies compared to sequential circuits, but takes advantage of the high
degree of parallelism inherent in such architectures to provide a favorable
tradeoff between throughput and energy efficiency at short to medium block
lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder
that combines the advantageous aspects of the combinational decoder with the
low-complexity nature of sequential-logic decoders. Performance characteristics
on ASIC and FPGA are presented with a detailed power consumption analysis for
combinational decoders. Finally, the paper presents an analysis of the
complexity and delay of combinational decoders, and of the throughput gains
obtained by hybrid-logic decoders with respect to purely synchronous
architectures.Comment: 12 pages, 10 figures, 8 table
Digital VLSI Architectures for Advanced Channel Decoders
Error-correcting codes are strongly adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probes. New and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity.
This work aims to focus on Polar codes, which are a recent class of channel codes with the proven ability to reduce decoding error probability arbitrarily small as the block-length is increased, provided that the code rate is less than the capacity of the channel. This property and the recursive code-construction of this algorithms attracted wide interest from the communications community.
Hardware architectures with reduced complexity can efficiently implement a polar codes decoder using either successive cancellation approximation or belief propagation algorithms. The latter offers higher throughput at high signal-to-noise ratio thanks to the inherently parallel decision-making capability of such decoder type. A new analysis on belief propagation scheduling algorithms for polar codes and on interconnection structure of the decoding trellis not covered in literature is also presented. It allowed to achieve an hardware implementation that increase the maximum information throughput under belief propagation decoding while also minimizing the implementation complexity