Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

Design and Testing of Electronic Devices for Harsh Environments

In this thesis an overview of the research activity focused on development, design and testing of electronic devices and systems for harsh environments has been reported. The scope of the work has been the design and validation flow of Integrated Circuits operating in two harsh applications: Automotive and High Energy Physics experiments. In order to fulfill the severe operating electrical and environmental conditions of automotive applications, a systematic methodology has been followed in the design of an innovative Intelligent Power Switch: several design solutions have been developed at architectural and circuital level, integrating on-chip selfdiagnostic capabilities and full protection against high voltage and reverse polarity, effects of wiring parasitics, over-current and over-temperature phenomena. Moreover current slope and soft start integrated techniques has ensured low EMI, making the Intelligent Power Switch also configurable to drive different interchangeable loads efficiently. The innovative device proposed has been implemented in a 0.35 μm HV-CMOS technology and embedded in mechatronic 3rd generation brush-holder regulator System-on-Chip for an automotive alternator. Electrical simulations and experimental characterization and testing at componentlevel and on-board system-level has proven that the proposed design allows for a compact and smart power switch realization, facing the harshest automotive conditions. The smart driver has been able to supply up to 1.5 A to various types of loads (e.g.: incadescent lamp bulbs, LED), in operating temperatures in the wide range -40 °C to 150 °C, with robustness against high voltage up to 55 V and reverse polarity up to -15 V. The second branch of research activity has been framed within the High Energy Physics area, leading to the development of a general purpose and flexible protocol for the data acquisition and the distribution of Timing, Trigger and Control signals and its implementation in radiation tolerant interfaces in CMOS 130 nm technology. The several features integrated in the protocol has made it suitable for different High Energy Physics experiments: flexibility w.r.t. bandwidth and latency requirements, robustness of critical information against radiation-induced errors, compatibility with different data types, flexibility w.r.t the architecture of the control and readout systems, are the key features of this novel protocol. Innovative radiation hardening techniques have been studied and implemented in the test-chip to ensure the proper functioning in operating environments with a high level of radiation, such as the Large Hadron Collider at CERN in Geneva. An FPGA-based emulator has been developed and, in a first phase, employed for functional validation of the protocol. In a second step, the emulator has been modified as test-bed to assess the Transmitter and Receiver interfaces embedded on the test-chip. An extensive phase of tests has proven the functioning of the interfaces at the three speed options, 4xF, 8xF and 16xF (F = reference clock frequency) in different configurations. Finally, irradiation tests has been performed at CERN X-rays irradiation facility, bearing out the proper behaviour of the interfaces up to 40 Mrad(SiO2)

Low-Power Wireless Distributed SIMD Architecture Concept: An 8051 Based Remote Execution Unit

Power has become a critical aspect in the design of modern wireless systems, especially in passive device nodes such as Radio Frequency Identification (RFID) tags, sensor nodes etc. Passive RFID tags in particular use simple logic that is used to respond with a unique code or data to identify objects when queried by an interrogator, whereas wireless passive sensor devices use microcontrollers for sensor data processing. There is a need for a Minimal Instruction Set Architecture (MISA) for such passive nodes with regard to low power. In this context, passive node capabilities need to be explored, possibly to suit target applications, in order to enable more than just identification and perhaps less than those of a conventional microcontroller Instruction Set Architecture (ISA). This dissertation research demonstrates a low-power wireless distributed processor architecture concept. The data and program instructions are stored on a powered interrogator providing wireless supervisory control for the remote passive node that has a basic processing core called the remote execution unit (REU). The interrogator and the passive node (REU) combination can be viewed as a complete processor or as multiple processing units forming the basis for a wireless distributed Single Instruction Multiple Data (SIMD) processor. This research introduces and investigates the REU architecture using an 8051-MISA with the goal of reducing power consumption of the system. A novel low power data-driven symbol decoder-CRC along with the 8051-MISA based execution core design form the frontend and core part of the REU architecture. Clocked and asynchronous digital logic implementations of the REU core design are presented and correspondingly the power, area and speed comparisons are also provided. Lack of strong support by commercial CAD tools is a major hurdle for synthesis of asynchronous designs. This research also presents a high-level design flow used to implement the asynchronous logic for the REU using traditional clocked CAD flows. This research work demonstrates immense potential to realize low power wireless passive sensor nodes for biomedical, automation, environmental, etc., applications especially while providing the basis for a programmable passive remote unit for distributed processing

Architectural-level Power Optimization of Microcontroller Cores in Embedded Systems

Power saving is becoming one of the major design drivers in electronic systems embedding microcontroller cores. Known microcontrollers typically save power at the expense of reduced computational capability. With reference to an 8051 core, this paper presents a novel clustered clock gating to increase power efficiency at architectural level without performance loss and preserving the reusability of the macrocell. Different from known clustered-gating strategies where the number of clusters is fixed a priori, the optimal cluster organization is derived, considering both the macrocell complexity and switching activity. When implementing the 8051 core in CMOS technology, the proposed approach leads to a 37% power saving, which is higher than the 29% permitted by automatic-clock-gating insertion in commercial computer-aided design tools or the 10% of state-of-the-art clustered-gating strategies. To assess its full functionality, the power-optimized cell has been proved in silicon that is embedded in an automotive system for sensors interface/contro