Flexible HW-SW design and analysis of an MMT-based MANET system on FPGA

Recently there has been a rapid growth of research interests in Mobile Ad-hoc Networks (MANETs). Their infrastructureless and dynamic nature demands that new strategies be implemented on a robust wireless communication platform in order to provide efficient end-to-end communication. Many routing algorithms have been developed to serve this purpose. This thesis investigated Multi-Meshed Tree (MMT) algorithm, an integrated solution that combines routing, clustering and medium access control operations based on a common multi-meshed tree concept. It provides the robustness and redundancy inherent in mesh topologies and uses the tree branches to deliver packets. MMT is the first of its kind that enables a single algorithm to form multiple proactive routes within a cluster while supporting reactive routes between different clusters. Recent published research and simulations have shown its favorable features and results. To explore the MMT algorithm\u27s novel feature in real systems against simulation work, this work adopts Field Programmable Gate Arrays (FPGA) as the platform for wireless system implementations. Full hardware and various System-on-Chip Hardware-Software designs are developed and studied, providing a design practice that contributes to low-cost system development in the field of MANET by utilizing the evolving FPGA technology. The results show that the MMT-based systems functioned accurately and effectively; in all proposed test scenarios they demonstrated many of the features that a desired MANET routing algorithm should have: high transmission success rate, low latency, scalability, few queued packets and low overhead. The results give valuable insights into the MMT algorithm\u27s performance and facilitate its future improvements

Multistage Switching Architectures for Software Routers

Software routers based on personal computer (PC) architectures are becoming an important alternative to proprietary and expensive network devices. However, software routers suffer from many limitations of the PC architecture, including, among others, limited bus and central processing unit (CPU) bandwidth, high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multistage PC-based architectures can be an interesting alternative since they permit us to i) increase the performance of single software routers, ii) scale router size, iii) distribute packet manipulation and control functionality, iv) recover from single-component failures, and v) incrementally upgrade router performance. We propose a specific multistage architecture, exploiting PC-based routers as switching elements, to build a high-speed, largesize,scalable, and reliable software router. A small-scale prototype of the multistage router is currently up and running in our labs, and performance evaluation is under wa

Branch Prediction For Network Processors

Originally designed to favour flexibility over packet processing performance, the future of the programmable network processor is challenged by the need to meet both increasing line rate as well as providing additional processing capabilities. To meet these requirements, trends within networking research has tended to focus on techniques such as offloading computation intensive tasks to dedicated hardware logic or through increased parallelism. While parallelism retains flexibility, challenges such as load-balancing limit its scope. On the other hand, hardware offloading allows complex algorithms to be implemented at high speed but sacrifice flexibility. To this end, the work in this thesis is focused on a more fundamental aspect of a network processor, the data-plane processing engine. Performing both system modelling and analysis of packet processing functions; the goal of this thesis is to identify and extract salient information regarding the performance of multi-processor workloads. Following on from a traditional software based analysis of programme workloads, we develop a method of modelling and analysing hardware accelerators when applied to network processors. Using this quantitative information, this thesis proposes an architecture which allows deeply pipelined micro-architectures to be implemented on the data-plane while reducing the branch penalty associated with these architectures

Reconfigurable network systems and software-defined networking

Modern high-speed networks have evolved from relatively static networks to highly adaptive networks facilitating dynamic reconfiguration. This evolution has influenced all levels of network design and management, introducing increased programmability and configuration flexibility. This influence has extended from the lowest level of physical hardware interfaces to the highest level of network management by software. A key representative of this evolution is the emergence of softwaredefined networking (SDN). In this paper, we review the current state of the art in reconfigurable network systems, covering hardware reconfiguration, SDN, and the interplay between them. We take a top-down approach, starting with a tutorial on software-defined networks. We then continue to discuss programming languages as the linking element between different levels of software and hardware in the network. We review electronic switching systems, highlighting programmability and reconfiguration aspects, and describe the trends in reconfigurable network elements. Finally, we describe the state of the art in the integration of photonic transceiver and switching elements with electronic technologies, and consider the implications for SDN and reconfigurable network systems.This work was jointly supported by the UKs Engineering and Physical Sciences Research Council (EPSRC) Internet Project EP/H040536/1, an EPSRC Research Fellowship grant to Philip Watts (EP/I004157/2), and DARPA and AFRL under contract FA8750-11-C-0249.This is the final version of the article. It first appeared from IEEE via http://dx.doi.org/10.1109/JPROC.2015.243573

The future roadmap of in-vehicle network processing: a HW-centric (R-)evolution

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The automotive industry is undergoing a deep revolution. With the race towards autonomous driving, the amount of technologies, sensors and actuators that need to be integrated in the vehicle increases exponentially. This imposes new great challenges in the vehicle electric/electronic (E/E) architecture and, especially, in the In-Vehicle Network (IVN). In this work, we analyze the evolution of IVNs, and focus on the main network processing platform integrated in them: the Gateway (GW). We derive the requirements of Network Processing Platforms that need to be fulfilled by future GW controllers focusing on two perspectives: functional requirements and structural requirements. Functional requirements refer to the functionalities that need to be delivered by these network processing platforms. Structural requirements refer to design aspects which ensure the feasibility, usability and future evolution of the design. By focusing on the Network Processing architecture, we review the available options in the state of the art, both in industry and academia. We evaluate the strengths and weaknesses of each architecture in terms of the coverage provided for the functional and structural requirements. In our analysis, we detect a gap in this area: there is currently no architecture fulfilling all the requirements of future automotive GW controllers. In light of the available network processing architectures and the current technology landscape, we identify Hardware (HW) accelerators and custom processor design as a key differentiation factor which boosts the devices performance. From our perspective, this points to a need - and a research opportunity - to explore network processing architectures with a strong HW focus, unleashing the potential of next-generation network processors and supporting the demanding requirements of future autonomous and connected vehicles.Peer ReviewedPostprint (published version

Systems And Methods For Intelligent Policy Enforcement In Access Networks

Systems and methods of intelligent policy enforcement in access networks are disclosed. One such method is implemented in a network device and comprises updating a traffic history with information associated with an incoming packet arriving from or destined to a subscriber link. The method also comprises calculating a drop probability for a next traffic instant and predicting a traffic rate for each of a plurality of flows on the subscriber link. The method also comprises determining whether the incoming packet conforms to a traffic policy associated with the incoming packet. The method also comprises determining whether surplus bandwidth is available on the subscriber link. The method also comprises forwarding the packet responsive to the determination that the incoming packet does not conform and that surplus bandwidth is available.Georgia Tech Research Corporatio