A Fast Simulation Method for Analysis of SEE in VLSI

The transistor simulation tools (e.g. TCAD and SPICE) are widely used to simulate single event effects (SEE) in industry. However, due to the variances of the physical parameters in practical design, e.g. the nature of the particle, linear energy transfer and circuit characteristics would have a large impacts on the final simulation accuracy, which will significantly increase the complexity and cost in the workflow of the transistor level simulation for large scale circuits. Therefore, a new SEE simulation scheme is proposed to offer a fast and cost-efficient method to evaluate and compare the performance of large scale circuits in the effects of radiation particles. In this work, we have combined both the advantages of transistor and hardware description language (HDL) simulations, and proposed accurate SEE digital error models for high-speed error analysis in the large scale circuits. The experimental results show that the proposed scheme is able to handle SEE simulations for more than 40 different circuits with the sizes varied from 100 transistors to 100 k transistors

Evaluation of creep behavior of geosynthetics using accelerated and conventional methods

Geosynthetics are susceptible to creep, which leads to time-dependent strains and potentially induces deformation of the structural systems. In the design of geosynthetics, one of the major issues is to apply the appropriate creep reduction factors. To evaluate the creep behavior of geosynthetics, four creep test methods were utilized in this study: Stepped Isothermal Method (SIM), Time-Temperature Superposition (TTS), Time-Temperature-Stress Superposition (TTSS), and a conventional method. SIM and TTS are accelerated creep methods by using elevated temperatures instead of a long testing duration. SIM particularly uses a single specimen throughout a sequence of elevated temperature tests and thus, material variability can be avoided in contrast to TTS. The procedure to generate a creep master curve in SIM was modified from that recommended by ASTM to account for thermal expansion of geosynthetics. TTSS imposes the stress effect to TTS and is suitable for polymers that have limitations in adopting TTS.In this study, three types of geosynthetics were tested: drainage components, i.e., high density polyethylene (HDPE) geonet and geocomposite, the expanded polystyrene (EPS) geofoam, and the polyethylene-terephthalate (PET) and HDPE geogrids. For the geonet and geocomposite, the tests were performed under compressive loads at different inclined angles to simulate the application in the side slope of the landfills. The results showed that the creep strains of the drainage components increased with inclined angles for both geonet and geocomposite. For the geonet, the secondary creep stage was found to coincide with the roll-over of upper ribs, indicating that the geometry of geonet had a strong influence to its creep behavior. Furthermore, the onset time of the secondary stage decreased as inclined angles increased. The creep behavior of the geocomposite was substantially different from that of the corresponding geonet, showing only primary creep stage. The absence of the secondary creep was due to the localized interface friction between the needle-punched nonwoven geotextile and the ribs. The friction prevented the abrupt roll-over phenomenon in the geonet.The compressive creep behavior of the EPS geofoam was investigated. A bilinear relationship between compressive strength and temperature with transition at 43oC had direct impact on the results of SIM and TTS. A premature secondary creep stage in comparison with a conventional method data and the change of activation energy were observed at test temperatures above 43oC. The alternative accelerated creep test, TTSS, was conducted at temperatures below 43oC and was found to be the most appropriate method for this geofoam.The tensile creep behavior of the PET and HDPE geogrids were evaluated, and the creep strains of the PET geogrid were much less than the HDPE geogrid at the same percentage of ultimate tensile strength. Also, the HDPE geogrid went through the primary, secondary and tertiary creep prior to the rupture, whereas only primary creep and rupture were detected in the PET geogrid. The activation energies of the PET geogrid were consistent regardless of the types of accelerated creep test methods. Contrary, higher activation energies were resulted from the short-term accelerated tests in comparison to the long-term tests for the HDPE geogrid. In order to develop the constitutive relationship, the Weibull model was modified. The results of model were well correlated to the experimental data.Ph.D., Civil Engineering -- Drexel University, 200

Analysis and Design of Resilient VLSI Circuits

The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation-induced soft errors. Among these noise sources, soft errors (or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as combinational logic circuits. Also, in the DSM era, process variations are increasing at an alarming rate, making it more difficult to design reliable VLSI circuits. Hence, it is important to efficiently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this dissertation presents several analysis and design techniques with the goal of realizing VLSI circuits which are tolerant to radiation particle strikes and process variations. This dissertation consists of two parts. The first part proposes four analysis and two design approaches to address radiation particle strikes. The analysis techniques for the radiation particle strikes include: an approach to analytically determine the pulse width and the pulse shape of a radiation induced voltage glitch in combinational circuits, a technique to model the dynamic stability of SRAMs, and a 3D device-level analysis of the radiation tolerance of voltage scaled circuits. Experimental results demonstrate that the proposed techniques for analyzing radiation particle strikes in combinational circuits and SRAMs are fast and accurate compared to SPICE. Therefore, these analysis approaches can be easily integrated in a VLSI design flow to analyze the radiation tolerance of such circuits, and harden them early in the design flow. From 3D device-level analysis of the radiation tolerance of voltage scaled circuits, several non-intuitive observations are made and correspondingly, a set of guidelines are proposed, which are important to consider to realize radiation hardened circuits. Two circuit level hardening approaches are also presented to harden combinational circuits against a radiation particle strike. These hardening approaches significantly improve the tolerance of combinational circuits against low and very high energy radiation particle strikes respectively, with modest area and delay overheads. The second part of this dissertation addresses process variations. A technique is developed to perform sensitizable statistical timing analysis of a circuit, and thereby improve the accuracy of timing analysis under process variations. Experimental results demonstrate that this technique is able to significantly reduce the pessimism due to two sources of inaccuracy which plague current statistical static timing analysis (SSTA) tools. Two design approaches are also proposed to improve the process variation tolerance of combinational circuits and voltage level shifters (which are used in circuits with multiple interacting power supply domains), respectively. The variation tolerant design approach for combinational circuits significantly improves the resilience of these circuits to random process variations, with a reduction in the worst case delay and low area penalty. The proposed voltage level shifter is faster, requires lower dynamic power and area, has lower leakage currents, and is more tolerant to process variations, compared to the best known previous approach. In summary, this dissertation presents several analysis and design techniques which significantly augment the existing work in the area of resilient VLSI circuit design