Quantum diffusion of microcavity solitons

Coherently pumped (Kerr) solitons in an ideal optical microcavity are expected to undergo random quantum motion that determines fundamental performance limits in applications of the soliton microcombs. Here this random walk and its impact on Kerr soliton timing jitter are studied experimentally. The quantum limit is discerned by measuring the relative position of counter-propagating solitons. Their relative motion features weak interactions and also presents common-mode suppression of technical noise, which typically hides the quantum fluctuations. This is in contrast to co-propagating solitons, which are found to have relative timing jitter well below the quantum limit of a single soliton on account of strong correlation of their mutual motion. Good agreement is found between theory and experiment. The results establish the fundamental limits to timing jitter in soliton microcombs and provide new insights on multisoliton physics

Spectral Efficiency and Energy Efficiency of OFDM Systems: Impact of Power Amplifiers and Countermeasures

In wireless communication systems, the nonlinear effect and inefficiency of power amplifier (PA) have posed practical challenges for system designs to achieve high spectral efficiency (SE) and energy efficiency (EE). In this paper, we analyze the impact of PA on the SE-EE tradeoff of orthogonal frequency division multiplex (OFDM) systems. An ideal PA that is always linear and incurs no additional power consumption can be shown to yield a decreasing convex function in the SE-EE tradeoff. In contrast, we show that a practical PA has an SE-EE tradeoff that has a turning point and decreases sharply after its maximum EE point. In other words, the Pareto-optimal tradeoff boundary of the SE-EE curve is very narrow. A wide range of SE-EE tradeoff, however, is desired for future wireless communications that have dynamic demand depending on the traffic loads, channel conditions, and system applications, e.g., high-SE-with-low-EE for rate-limited systems and high-EE-with-low-SE for energy-limited systems. For the SE-EE tradeoff improvement, we propose a PA switching (PAS) technique. In a PAS transmitter, one or more PAs are switched on intermittently to maximize the EE and deliver an overall required SE. As a consequence, a high EE over a wide range SE can be achieved, which is verified by numerical evaluations: with 15% SE reduction for low SE demand, the PAS between a low power PA and a high power PA can improve EE by 323%, while a single high power PA transmitter improves EE by only 68%.Comment: to be published, IEEE J. Sel. Areas Commu

Application of advanced on-board processing concepts to future satellite communications systems: Bibliography

Abstracts are presented of a literature survey of reports concerning the application of signal processing concepts. Approximately 300 references are included

Models predicting the performance of IC component or PCB channel during electromagnetic interference

This dissertation is composed of three papers, which cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference. In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter de-convolution method is also presented for extracting the characteristics of crosstalk induced jitter from measurements of total jitter made when the crosstalk sources were and were not present. The proposed techniques are shown to work well both in simulations and in measurements of a high-speed link. In the second paper, methods are developed to predict the statistical distribution of timing jitter due to dynamic currents drawn by an integrated circuit (IC) and the resulting power supply noise on the PCB. Distribution of dynamic currents is found through vectorless methods. Results demonstrate the approach can rapidly determine the average and standard deviation of the power supply noise voltage and the peak jitter within 5~15% error, which is more than sufficient for predicting the performance impact on integrated circuits. In the third paper, a model is developed to predict the susceptibility of a DLL to electromagnetic noise on the power supply. With the proposed analytical noise transfer function, peak to peak jitter and cycle to cycle jitter at the DLL output can be estimated, which can be use to predict when soft failures will occur and to better understand how to fix these failures. Simulation and measurement results demonstrate the accuracy of the DLL delay model. --Abstract, page iv

Power Side Channels in Security ICs: Hardware Countermeasures

Power side-channel attacks are a very effective cryptanalysis technique that can infer secret keys of security ICs by monitoring the power consumption. Since the emergence of practical attacks in the late 90s, they have been a major threat to many cryptographic-equipped devices including smart cards, encrypted FPGA designs, and mobile phones. Designers and manufacturers of cryptographic devices have in response developed various countermeasures for protection. Attacking methods have also evolved to counteract resistant implementations. This paper reviews foundational power analysis attack techniques and examines a variety of hardware design mitigations. The aim is to highlight exposed vulnerabilities in hardware-based countermeasures for future more secure implementations

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Modeling and analysis of power processing systems: Feasibility investigation and formulation of a methodology

A review is given of future power processing systems planned for the next 20 years, and the state-of-the-art of power processing design modeling and analysis techniques used to optimize power processing systems. A methodology of modeling and analysis of power processing equipment and systems has been formulated to fulfill future tradeoff studies and optimization requirements. Computer techniques were applied to simulate power processor performance and to optimize the design of power processing equipment. A program plan to systematically develop and apply the tools for power processing systems modeling and analysis is presented so that meaningful results can be obtained each year to aid the power processing system engineer and power processing equipment circuit designers in their conceptual and detail design and analysis tasks