Study Of Ingaas Ldmos For Power Conversion Applications

In this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-µm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways, structure with the same cross-sectional dimension, and structure with different thickness of gate dielectric to achieve the same gate capacitance. The on-resistance of the new device shows a big improvement with no degradation on breakdown voltage over traditional device. Also it is indicated from these comparisons that the figure of merit(FOM) Ron·Qg of In0.65Ga0.35As LDMOS shows an average of 91.9% improvement to that of Si LDMOS. To further explore the benefit of using In0.65Ga0.35As LDMOS as switch in power applications, DC-DC buck converter is utilized to observe the performance of LDMOS in terms of power efficiency. The LDMOS performance is experimented with operation frequency of the circuit sweeping in the range from 100 KHz to 100 MHz. It turns out InGaAs LDMOS is good candidate for power applications

Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology

Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states

Conception, fabrication, caractérisation et modélisation de transistors MOSFET haute tension en technologie avancée SOI (Silicon-On-Insulator)

Nowadays the scaling of bulk silicon CMOS technologies is reaching physical limits. In this context, the FDSOI technology (fully depleted silicon-on-insulator) becomes an alternative for the industry because of its superior performances. The use of an ultra-thin SOI substrate provides an improvement of the MOSFETs behaviour and guarantees their electrostatic integrity for devices of 28nm and below. The development of high-voltage applications such DC/DC converters, voltage regulators and power amplifiers become necessary to integrate new functionalities in the technology. However, the standard devices are not designed to handle such high voltages. To overcome this limitation, this work is focused on the design of a high voltage MOSFET in FDSOI. Through simulations and electrical characterizations, we are exploring several solutions such as the hybridization of the SOI substrate (local opening of the buried oxide) or the implementation in the silicon film. An innovative architecture on SOI, the Dual Ground Plane EDMOS, is proposed, characterized and modelled. It relies on the biasing of a dedicated ground plane introduced below the device to offer promising RON.S/BV trade-off for the targeted applications.A l’heure où la miniaturisation des technologies CMOS sur substrat massif atteint des limites, la technologie FDSOI (silicium sur isolant totalement déserté) s’impose comme une alternative pour l’industrie en raison de ses meilleures performances. Dans cette technologie, l’utilisation d’un substrat SOI ultramince améliore le comportement des transistors MOSFETs et garantit leur intégrité électrostatique pour des dimensions en deçà de 28nm. Afin de lui intégrer de nouvelles fonctionnalités, il devient nécessaire de développer des applications dites « haute tension » comme les convertisseurs DC/DC, les régulateurs de tension ou encore les amplificateurs de puissance. Cependant les composants standards de la technologie CMOS ne sont pas capables de fonctionner sous les hautes tensions requises. Pour répondre à cette limitation, ces travaux portent sur le développement et l’étude de transistors MOS haute tension en technologie FDSOI. Plusieurs solutions sont étudiées à l’aide de simulations numériques et de caractérisations électriques : l’hybridation du substrat (gravure localisée de l’oxyde enterré) et la transposition sur le film mince. Une architecture innovante sur SOI, le Dual Gound Plane EDMOS, est alors proposée, caractérisée et modélisée. Cette architecture repose sur la polarisation d’une seconde grille arrière pour offrir un compromis RON.S/BV prometteur pour les applications visées