Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event

In this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide-Semiconductor (DMOS) process are used for design of experiment. A multi-function test platform High Power Pulse Instrument (HPPI) is used for ESD event evaluation and device characterization. SPICE-like software ADICE is for back-end simulation. Electrostatic Discharges (ESD) is one of the hazard that may affect IC circuit function and cause serious damage to the chip. The importance of ESD protection has been raised since the CMOS technology advanced and the dimension of transistors scales down. On the other hand, the variety of applications of chips is also making corresponding ESD protection difficult to meet different design requirement. Aside from typical requirements such as core circuit operation voltage, maximum accepted leakage current, breakdown conditions for the process and overall device sizes, special applications like radio frequency and power electronic requires ESD to be low parasitic capacitance and can sustain high level energy. In that case, a proper ESD protection design demands not only a robust ESD protection scheme, but co-design with the inner circuit. For that purpose, it is necessary to simulate the results of ESD impact on IC and find out possible weak point of the circuit and improve it. The first step of the simulation is to have corresponding models available. Unfortunately, ESD models, especially there are lack of circuit-level ESD models that provide quick and accurate prediction of ESD event. In this dissertation paper, ESD models, especially ESD failure models for device thermal failure are introduced, with modeling methodology accordingly. First, an introduction for ESD event and typical ESD protection schemes are introduced. Its purpose is to give basic concept of ESD. For ESD failure models, two typical types can be categorized depends on the physical mechanisms that cause the ESD damage. One is the gate oxide breakdown, which is electric field related. The other is the thermal-related failure, which stems from the self-heating effect associated with the large current passing through the ESD protection structure. The first one has become increasingly challenging with the aggressive scaling of the gate dielectric in advanced processes and ESD protection for that need to be carefully designed. The second one, thermal failure widely exists in semiconductor devices as long as there is ESD current flow through the device and accumulate heat at junctions. Considering the universality of thermal failure in ESD device, it is imperative to establish a model to simulate ESD caused thermal failure. Several works related to ESD model can be done. One crucial part for a failure model is to define the failure criterion. As common solution for ESD simulation and failure prediction. The maximum current level or breakdown voltage is used to judge whether a device fails under ESD stresses. Such failure criteria based on measurable voltage or current values are straightforward and can be easy to implemented in simulation tools. However, the shortcoming of these failure criteria is each failure criterion is specifically designed for certain ESD stress condition. For example, the failure voltage level for Human Body Model and Charged Device Model are quite different, and it is hard to judge a device\u27s ESD capability under standard test conditions based on its transmission line pulse test result. So it is necessary to look deeper into the physical mechanism of device failure under ESD and find a more universal failure criterion for various stress conditions. As one of the major failure mechanisms, thermal failure evaluated by temperature is a more universal failure criterion for device failure under ESD stress. Whatever the stress model is, the device will fail if a critical temperature is reached at certain part inside the device and cause structural damage. Then finding out that critical temperature is crucial to define the failure point for device thermal failure. One chapter of this dissertation will focus on discussing this issue and propose a simple method to give close estimation of the real failure temperature for typical ESD devices. Combined these related works, a comprehensive diode model for ESD simulation is proposed. Using existing ESD models, diode I-V characteristic from low current turn-on to high current saturation can be simulated. By using temperature as the failure criterion, the last point of diode operation, or the second breakdown point, can be accurately predicted. Additional investigation of ESD capability of devices for special case like vertical GaN diode is discussed in Chapter IV. Due to the distinct material property of GaN, the vertical GaN diode exhibits unique and interesting quasi-static I-V curves quite different from conventional silicon semiconductor devices. And that I-V curve varies with different pulse width, indicating strong conductivity modulation of diode neutral region that will delay the complete turn-on of the vertical GaN diode

CMOS RF low noise amplifier with high ESD immunity.

Tang Siu Kei.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 107-111).Abstracts in English and Chinese.Acknowledgements --- p.iiAbstract --- p.iiiList of Figures --- p.xiList of Tables --- p.xviChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4Chapter 1.3 --- Research Goal and Contribution --- p.6Chapter 1.4 --- Thesis Outline --- p.6Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8Chapter 2.1 --- Amplifier Gain --- p.8Chapter 2.2 --- Noise Factor --- p.9Chapter 2.3 --- Linearity --- p.11Chapter 2.3.1 --- 1-dB Compression Point --- p.13Chapter 2.3.2 --- Third-Order Intercept Point --- p.14Chapter 2.4 --- Return Loss --- p.16Chapter 2.5 --- Power Consumption --- p.18Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21Chapter 3.1 --- Dual-Diode Circuitry --- p.22Chapter 3.1.1 --- Working Principle --- p.22Chapter 3.1.2 --- Drawbacks --- p.24Chapter 3.2 --- Shunt-Inductor Method --- p.25Chapter 3.2.1 --- Working Principle --- p.25Chapter 3.2.2 --- Drawbacks --- p.27Chapter 3.3 --- Common-Gate Input Stage Method --- p.28Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29Chapter 3.3.2 --- Competitiveness --- p.31Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32Chapter 4.1 --- Small-Signal Modeling --- p.33Chapter 4.2 --- Method of Input Termination --- p.33Chapter 4.2.1 --- Resistive Termination --- p.34Chapter 4.2.2 --- Shunt-Series Feedback --- p.34Chapter 4.2.3 --- l/gm Termination --- p.35Chapter 4.2.4 --- Inductive Source Degeneration --- p.36Chapter 4.3 --- Method of Gain Enhancement --- p.38Chapter 4.3.1 --- Tuned Amplifier --- p.38Chapter 4.3.2 --- Multistage Amplifier --- p.40Chapter 4.4 --- Improvement of Reverse Isolation --- p.41Chapter 4.4.1 --- Common-Gate Amplifier --- p.41Chapter 4.4.2 --- Cascoded Amplifier --- p.42Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55Chapter 6.2 --- Design of Two-Stage Architecture --- p.57Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59Chapter 6.3 --- Stability Consideration --- p.61Chapter 6.4 --- Design of Matching Networks --- p.62Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67Chapter Chapter 7 --- Layout Considerations --- p.70Chapter 7.1 --- MOS Transistor --- p.70Chapter 7.2 --- Capacitor --- p.72Chapter 7.3 --- Spiral Inductor --- p.74Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81Chapter Chapter 8 --- Measurement Results --- p.82Chapter 8.1 --- Experimental Setup --- p.82Chapter 8.1.1 --- Testing Circuit Board --- p.83Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89Chapter 8.2.1 --- S-parameter Measurement --- p.90Chapter 8.2.2 --- Noise Figure Measurement --- p.91Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93Chapter 8.2.5 --- HBM ESD Test --- p.94Chapter 8.2.6 --- Summary of Measurement Results --- p.95Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96Chapter 8.3.1 --- s-parameter Measurement --- p.97Chapter 8.3.2 --- Noise Figure Measurement --- p.98Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100Chapter 8.3.5 --- HBM ESD Test --- p.101Chapter 8.3.6 --- Summary of Measurement Results --- p.102Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103Chapter Chapter 9 --- Conclusion and Future Work --- p.105Chapter 9.1 --- Conclusion --- p.105Chapter 9.2 --- Future Work --- p.106References --- p.107Author's Publications --- p.11