A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Switched capacitor networks : a novel prewarping procedure

Bibliography: leaves 152-157.Novel methods for prewarping filter specifications prior to realization. in Switched Capacitor (SC) form are presented. These allow the design of arbitrary response requirements, exhibiting a low amount of error that normally results from the frequency warping associated with sampled-data networks. Adjustment is applied to the pole and zero locations of a reference filter, using three distinct approaches (Center frequency "CF", Selectivity "S" and Complex Mapping "CM" pole/zero prewarping), developed for both the Lossless Discrete Integrator (LOI) and Bilinear (Bil) analog to digital transformations. The derivation of the prewarping expressions is explained with reference to these mappings, and the effect they have on the apparent pole and zero locations of an SC filter realization

Sampled data systems and generating functions

Application of Z-transforms to sampled-data system

Fractional order chaotic systems and their electronic design

"Con el desarrollo del cálculo fraccionario y la teoría del caos, los sistemas caóticos de orden fraccionario se han convertido en una forma útil de evaluar las características de los sistemas dinámicos. En esta dirección, esta tesis es principalmente relacionada, es decir, en el estudio de sistemas caóticos de orden fraccionario, basado en sistemas disipativos de inestables, un sistema disipativo de inestable de orden fraccionario es propuesto. Algunas propiedades dinámicas como puntos de equilibrio, exponentes de Lyapunov, diagramas de bifurcación y comportamientos dinámicos caóticos del sistema caótico de orden fraccionario son estudiados. Los resultados obtenidos muestran claramente que el sistema discutido presenta un comportamiento caótico. Por medio de considerar la teoría del cálculo fraccionario y simulaciones numéricas, se muestra que el comportamiento caótico existe en el sistema de tres ecuaciones diferenciales de orden fraccionario acopladas, con un orden menor a tres. Estos resultados son validados por la existencia de un exponente positivo de Lyapunov, además de algunos diagramas de fase. Por otra parte, la presencia de caos es también verificada obteniendo la herradura topológica. Dicha prueba topológica garantiza la generaci´n de caos en el sistema de orden fraccionario propuesto. En orden de verificar la efectividad del sistema propuesto, un circuito electrónico es diseñado con el fin de sintetizar el sistema caótico de orden fraccionario.""With the development of fractional order calculus and chaos theory, the fractional order chaotic systems have become a useful way to evaluate characteristics of dynamical systems and forecast the trend of complex systems. In this direction, this thesis is primarily concerned with the study of fractional order chaotic systems, based on an unstable dissipative system (UDS), a fractional order unstable dissipative system (FOUDS) is proposed. Dynamical properties, such as equilibrium points, Lyapunov exponents, bifurcation diagrams and phase diagrams of the fractional order chaotic system are studied. The obtained results shown that the fractional order unstable dissipative system has a chaotic behavior. By utilizing the fractional calculus theory and computer simulations, it is found that chaos exists in the fractional order three dimensional system with order less than three. The lowest order to yield chaos in this system is 2.4. The results are validated by the existence of one positive Lyapunov exponent, phase diagrams; Besides, the presence of chaos is also verified obtaining the topological horseshoe. That topological proof guarantees the chaos generation in the proposed fractional order unstable dissipative system. In order to verify the effectiveness of the proposed system, an electronic circuit is designed with the purpose of synthesize the fractional order chaotic system, the fractional order integral is realized with electronic circuit utilizing the synthesis of a fractance circuit. The realization has been done via synthesis as passive RC circuits connected to an operational amplifier. The continuos fractional expansion have been utilized on fractional integration transfer function which has been approximated to integer order rational transfer function considering the Charef Method. The analogue electronics circuits have been simulated using HSPICE.

General rational approximation of Gaussian wavelet series and continuous-time gm-C filter implementation

© 2020 John Wiley & Sons, Ltd. This is the accepted version of the following article: Li, M, Sun, Y. General rational approximation of Gaussian wavelet series and continuous‐time g m ‐C filter implementation. Int J Circ Theor Appl. 2020; 1– 17., which has been published in final form at https://doi.org/10.1002/cta.2834.A general method of rational approximation for Gaussian wavelet series and Gaussian wavelet filter circuit design with simple gm-C integrators is presented in this work. Firstly, the multi-order derivatives of Gaussian function are analysed and proved as wavelet base functions. Then a high accuracy general approximation model of Gaussian wavelet series is constructed and the transfer function of first order derivative of Gaussian wavelet filter is obtained using quantum differential evolution (QDE) algorithm. Thirdly, as an example, a 5th order continuous-time analogue first order derivative of Gaussian wavelet filter circuit is designed based on multiple loop feedback structure with simple gm-C integrator as the basic blocks. Finally, simulation results demonstrate the proposed method is an excellent way for the wavelet transform implementation. The designed first order derivative of Gaussian wavelet filter circuit operates from a 0.53V supply voltage and a bias current 2.5nA. The power dissipation of the wavelet filter circuit at the basic scale is 41.1nW. Moreover, the high accuracy QRS detection based on the designed wavelet filter has been validated in application analysis.Peer reviewe

RF MEMS reference oscillators platform for wireless communications

A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device

Opamp-based synthesis of a fractional order switched system

"The analysis, design and circuit synthesis of a fractional order switched system is presented in this paper. That system is capable of showing chaotic oscillations with a fractional order less than three, i.e., 2.4. The dynamical system is called fractional order unstable dissipative system (FOUDS); because it consists of a switching law to display strange attractors. Its dynamical behavior is explored and a circuit synthesis system is realized considering operational amplifiers. SPICE simulations agree with the numerical results.