A +20dBm highly efficient linear outphasing Class-E PA without AM/AM and AM/PM characterization requirements

Outphasing Class-E Power Amplifiers (OEPAs) using isolating power combiners and an inverse cosine signal component separator are inherently linear but suffer from low efficiency at power back-off. For high efficiency both at maximum output power and at power back-off, non-isolating power combiners are required. In this work the linearity of OEPAs using nonisolating power combiners is studied theoretically and validated by measurement of a 1.8GHz 20dBm OEPA implemented in a standard 65nm CMOS technology using an off-chip transmissionline based combiner. The developed theoretical model for the linearity is then employed to define digital pre-distortion (DPD) parameters for the implemented OEPA. Using this theory-based DPD and without any AM/AM and AM/PM characterizations, -31dB RMS EVM level and below -30dB ACLR were measured for a 13.1dBm 6.25MHz 30Mbit/s 7dB PAPR 64QAM signal with 41.8% drain efficiency and 33.6% power added efficiency

Multi-Band Outphasing Power Amplifier Design for Mobile and Base Stations

New generations of wireless communication systems require linear efficient RF power amplifiers (PAs) for higher transmission data rates and longer battery life. On the contrary, conventional PAs are normally designed for peak efficiency under maximum output power (Pout). Thus, in power back-off, the overall efficiency degrades significantly and the average efficiency is much lower than the efficiency at maximum Pout. Chireix outphasing PA, also called LINC (Linear amplification using Non-linear Components), is one of the most promising techniques to improve the efficiency at power back-off. In this method, a variable envelope input signal is first decomposed into two constant-envelope phase-modulated signals and then amplified using two highly efficient non-linear PAs. The output signals are combined preferably in a loss-less power combiner to build the desired output signal. In this way, the PA exhibits high efficiency with good linearity. In this thesis, first we analyze a complex model of outphasing combiner considering its nonidealities such as reflection and loss in transmission lines (TL). Then we propose a compact model with analytical formula that is validated through several comparative tests using ADS and Spectre RF. Furthermore, we analyze the effect of reactive load in Chireix combiner with stubs (a parallel inductor and capacitor), while distinguishing between its capacitive and inductive parts. It is demonstrated that only the capacitive part of the reactive load degrades the performances. Based on this, a new architecture (Z LINC) is proposed where the power combiner is designed to provide a zero capacitive load to the PAs whatever the outphasing angle. The theory describing the operations of the system is developed and a 900 MHz classical LINC and Z-LINC PAs are designed and measured. In addition, a miniaturization technique is proposed which employs λ/8 or smaller TLs instead of conventional λ/4 TLs in outphasing power combiner. This technique is applied to implement a 900 MHz PA using LDMOS power transistors. Besides single-band PAs, dual-band PAs are more and more needed because of an increasing demand for wireless communication terminals to handle multi-band operation. In chapter 5, a new compact design approach for dual-band transmitters based on a reconfigurable outphasing combiner is proposed. The objective is to avoid the cumbersome implementations where several PAs and matching network are used in parallel. The technique is applied to design a dual band PA with a fully integrated power combiner in 90 nm CMOS technology. An inverter-based class D PA topology, particularly suitable for outphasing and multimode operations is presented. The TLs in the combiner, realized using a network of on-chip series inductors and parallel capacitors, are reconfigurable from λ/4 in 1800 MHz to λ/8 in 900 MHz. In order to maximize the efficiency, the on-chip inductors are implemented using high quality factor on chip slab inductors. The measured maximum Pout at 900/1800 MHz are 24.3 and 22.7 dBm with maximum efficiencies of 51% and 34% respectively

High Efficiency Microwave Amplifiers and SiC Varactors Optimized for Dynamic Load Modulation

The increasing use of mobile networks as the main source of internet connectivity is creating challenges in the infrastructure. Customer demand is a moving target and continuous hardware developments are necessary to supply higher data rates in an environmentally sustainable and cost effective way. This thesis reviews and advances the status of realizing wideband and high efficiency power amplifiers, which will facilitate improvements in network capacity and energy efficiency. Several demonstrator PAs are proposed, analyzed, designed, and characterized: First, resistive loading at higher harmonics in wideband power amplifier design suitable for envelope tracking (ET) is proposed. A 40 dBm decade bandwidth 0.4–4.1 GHz PA is designed, with 10–15 dB gain and 40–62% drain efficiency. Its versatility is demonstrated by digital pre-distortion (DPD) linearized measurements resulting in adjacent channel leakage ratios (ACLR) lower than −46 dBc for various downlink signals (WCDMA, LTE, WiMAX). Second, a theory for class-J microwave frequency dynamic load modulation (DLM) PAs is derived. This connects transistor technology and load network requirements to enable power-scalable and bandwidth conscious designs. A 38 dBm PA is designed at 2.08 GHz, maintaining efficiencies >45% over 8 dB of output power back-off (OPBO) dynamic range. From this pre-study a fully packaged 86-W peak power version at 2.14 GHz is designed. ACLR after DPD is −46 dBc at a drain efficiency of 34%. For DLM PAs there is a need for varactors with large effective tuning range and high breakdown voltage. For this purpose, SiC Schottky diode varactors are developed with an effective tuning range of 6:1 and supporting a 3:1 tuning ratio at 36 V of RF swing. Nonlinear characterization to enable Q-factor extraction in the presence of distortion is proposed and demonstrated by multi-harmonic active source- and load-pull, offering insights to tunable network design. Third, a method to evaluate and optimize dual-RF input PAs, while catering to higher harmonic conditions and transistor parasitics, is proposed. The method is validated by a PA design having a peak power of 44 +/- 0.9 dBm and 6 dB OPBO PAE exceeding 45% over a 1–3 GHz bandwidth. The results in this thesis contribute with a novel device and analysis of high efficiency and wideband PAs, aiding in the design of key components for future energy efficient and high capacity wireless systems

Class-E Power Amplifiers in Modern RF Transmitters

Power amplifiers have been playing a vital role in most wireless communication systems. In order to improve efficiency of wireless systems, advanced transmitter architectures, such as Doherty amplifiers, outphasing amplifiers, supply voltage modulation techniques are widely used. The goal of this work is to develop novel techniques for building load modulation transmitters based on class-E power amplifiers. The first contribution is an analytical model for derivation load network parameters. The proposed model derives the parameters for both the peak and back-off power levels providing high efficiency. The proposed model demonstrates, that class-E PA with shunt capacitance and shunt filter is capable of providing high drain efficiency for back-off output power levels. The second contribution is a design of a wideband class-E power amplifier (PA) with shunt capacitance and shunt filter. The broadband operation has been achieved by application of the double reactance compensation technique. Simulated and experimental results are presented. The performance of the fabricated PA is compared with existing wideband PAs. The third contribution is application of the proposed technique to outphasing PA design. The designed outphasing PA was optimized, fabricated and tested. A possibility to extend the operational bandwidth of the PA is considered. Also the application of the proposed technique to Doherty PA design is demonstrated. The fourth contribution is linearization of outphasing PA. Firstly, an analytical model describing the nonlinearity of nonisolated combiners under amplitude imbalance is presented. Secondly, a novel phase-only predistortion technique for class-E outphasing PAs is proposed. Thirdly, linearization of the fabricated outphasing PA based on memory polynomial model is demonstrated using a 64QAM OFDM modulated signal with 20 MHz bandwidth. Overall, this work provides novel techniques for load modulation transmitter design based on class-E power amplifiers with shunt capacitance and shunt filter

LINC based amplifier architectures for power efficient wireless transmitters

Wireless communication trends Performance measuring of a communication system Power amplifiers and transmitters Power efficiency enhancement techniques Design and Optimization of LINC transmitter for OFDM applications LINC concept LINC signal decomposition LINC efficiency and combiner technologies Design optimization of LINC system Mismatch (imbalance) effects Advanced LINC transmitter architectures The 2X1 LINC transmitter system The 2X2 LINC transmitter system Mismatch effects

Design of linear transmitters for wireless applications

Wireless standards for high data-rate communications typically employ complex modulation schemes that have large peak-to-average power ratios (PAPR), along with a significant bandwidth requirement. Transmitters for such applications often employ off-chip power amplifiers (PAs), that are typically operated in back-off, such that the peak output power is less than the output 1-dB compression point (P1dB), in order to minimize distortion. In mobile systems, architectures that can enhance the linearity of the transmit chain are highly attractive since these can reduce the PA's back-off requirement, which helps to enhance efficiency. In this dissertation, linearization techniques for mobile transmitters are explored. A Cartesian feedback-feedforward transmitter is proposed for linearity enhancement. The transmit path in the architecture is placed in a Cartesian feedback loop. The feedback error signal is applied to a Cartesian feedforward path for further linearity improvement. Linearity of the feedback-feedforward system is analyzed by using a Volterra series representation. System simulations using two-tone signals and modulated signals are also presented and are used to verify the linearity enhancement provided by the proposed architecture. A prototype transmitter IC that employs the Cartesian feedback-feedforward approach is implemented in a 0.13 μm CMOS process. Design considerations for critical transmitter circuits are discussed. A proof-of-concept Cartesian feedback-feedforward architecture that includes the prototype IC and external components is demonstrated. The implementation allows for a 8.7 dB improvement in the adjacent channel leakage ratio (ACLR), compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16-QAM LTE signal with 1.4 MHz bandwidth. The linearity of the Cartesian feedback-feedforward system is found to depend primarily on the loop gain of the Cartesian feedback and the linearity of the Cartesian feedforward path, which introduces a trade-off with power consumption. To enhance the linearity of the Cartesian feedback-feedforward transmitter even further within the Cartesian feedback loop, two modified Cartesian feedback-feedforward architectures are explored. System simulations show that both modified configurations can help to enhance linearity compared to the above Cartesian feedback-feedforward transmitter.Electrical and Computer Engineerin

Efficiency enhancement techniques for RF and millimeter wave power amplifiers

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 123-126).Power amplifiers are the circuit blocks in wireless transceivers that require the largest power budget because of their relatively low efficiencies. RF designers cannot depend solely on the development better semiconductor devices in advanced deeply scaled process technologies to obtain improved power amplifier performance. The development of new and better circuits, architectures and design methodologies to maximally exploit the available semiconductor devices is very important as well. This thesis investigates a number of techniques that can be used to improve the efficiency of power amplifiers and break the power-frequency tradeoff in power amplifier design. The first technique emphasizes the use of a class E tuned output network as an efficiency enhancement tool for power amplifiers regardless of their bias conditions. A Class E tuned CMOS power amplifier (PA) operating in the 60 GHz band was designed. Design, layout, and parasitic modeling considerations to attain high-efficiency millimeter-wave PA operation are discussed. Both single-ended and differential versions of the single-stage PA were implemented in a 32 nm SOI CMOS process. Peak power added efficiency of 27% (30%), power gain of 8.8 dB (10 dB), and saturated output power > 9 dBm (12.5 dBm) were measured at 60 GHz from the single-ended (differential) PA with 0.9 V supply. The second technique investigated the efficacy of resistance compression networks in an energy recycling network operating at multi-gigahertz frequencies. The resistance compression network reduces the variation in resonant rectifier input impedance seen at the isolation port of an isolating power combiner. The system was operated at 2.14 GHz and was built around Schottky barrier diodes custom fabricated in a 0.13 [mu]m CMOS process. It is the first experimental demonstration that resistance compression networks can be used for energy recycling in multi-gigahertz applications.by Olumuyiwa Temitope Ogunnika.Ph.D