Design of a 10GHz RF power amplifier in 130nm CMOS technology based on Wilkinson combiner methodology

There is a growing demand today to design and fabricate RF power amplifiers at high frequencies above 5GHz that can directly drive a 50Ω antenna with sufficiently high transmission power to meet the needs of various wireless communication applications. This has typically been done by using GaN or other III-V technologies to build the power amplifier transistor, in order to allow for the use of much higher power supply voltages, than are used in today’s silicon technologies. For example, a 5W GaN power amplifier at 5GHz would typically make use of a VDD of 5V to 10V, and would be done as a discrete device on a separate module from the RF analog circuitry built out of silicon. With the continuing evolution of Moore’s Law, silicon technologies in use today for high frequency wireless communications typically are using VDD of 1.5V or less. There is a desire, however, in many wireless applications to be able to place the RF power amplifier on the same silicon chip as all the other RF/analog IC circuitry, in order to save chip fabrication cost. Consequently, research in improved methods of RF power amplifier design in silicon technology is being done in many IC design laboratories in order to increase the RF power output of power amplifiers built in silicon. This MS Thesis proposes the complete design of a four channel RF power amplifier by using the Wilkinson combiner with 27dBm output power. All the circuits are designed and implemented based on the Global Foundries 130nm SiGe BiCMOS technology and design kit at a frequency of 10GHz with a VDD = 1.5V, to provide 0.5W of RF output signal power into a 50Ω antenna

Design of zigbee transmitter for IEEE 802.15.4 standrad

ZigBee is a standard defines a set of communication protocols for low-data-rate short-range wireless networking. ZigBee-based wireless devices operate in 868 MHz, 915 MHz, and 2.4 GHz frequency bands. The maximum data rate is 250 K bits per second. ZigBee is mainly for battery-powered applications where low data rate, low cost, and long battery life are main requirements. This thesis explores low power RFIC design for various blocks in Zigbee Transmitter. Zigbee RFTransmitter Comprises of Low Pass Filter, Variable Gain Amplifier, Up conversion Mixer and Power Amplifier. The proposed VGA is characterized by a wide range of gain variation The single-stage VGA is designed in UMC 0.18-u m CMOS technology and shows the maximum gain variation of 62 dB. The VGA dissipates 630 uA from 1.8-V supply while occupying (250 μm x 167.3 μm) of chip area. A low-voltage low-power and high linearity up-conversion mixer, designed in UMC 0.18-um RFCMOS technology is proposed to realize the transmitter front-end in the frequency band of 2.45 GHz. The proposed mixer can convert a 5 MHz intermediate frequency (IF) signals to a 2.45GHz RF signals, with a local oscillator at 2.45GHz. Simulation results demonstrate that at 2.45GHz, the circuit provides -11.30dB of conversion gain and the input-referred third-order intercept point (IIP3) of 35.16 dBm, output-referred third order intercept point(OIP3) of 12.88 dBm while drawing only 10mA for the mixer core under a supply voltage of 1.8 V. A low power Differential class A power amplifier is designed in the UMC 0.18um RFCMOS technology. The class A power amplifier provides 0 dBm output power with a power-added efficiency (PAE) of 22% and Power Gain of 10dB with 1.8V supply voltage. The dc power consumption is only 4.5mW. And all these blocks were integrated and simulated using Cadence© SpectreRF simulator in UMC-0.18um Mixed Signal CMOS RF models for the best simulation results