Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

RF Circuit linearity optimization using a general weak nonlinearity model

This paper focuses on optimizing the linearity in known RF circuits, by exploring the circuit design space that is usually available in today’s deep submicron CMOS technologies. Instead of using brute force numerical optimizers we apply a generalized weak nonlinearity model that only involves AC transfer functions to derive simple equations for obtaining design insights. The generalized weak nonlinearity model is applied to three known RF circuits: a cascode common source amplifier, a common gate LNA and a CMOS attenuator. It is shown that in deep submicron CMOS technologies the cascode transistor in both the common source amplifier and in the common gate amplifier significantly contributes IM3 distortion. Some design insights are presented for reducing the cascode transistor related distortion, among which moderate inversion biasing that improves IIP3 by 10 dB up to 5 GHz in a 90 nm CMOS process. For the attenuator, a wideband IM3 cancellation technique is introduced and demonstrated using simulations

RF techniques for IEEE 802.15.4: circuit design and device modelling

The RF circuitry in the physical layer of any wireless communication node is arguably its most important part. The front-end radio is the hardware that enables communication by transmitting and receiving information. Without a robust and high performance front-end, all other higher layers of signal processing and data handling in a wireless network are irrelevant. This thesis investigates the radio circuitry of wireless-networked nodes, and introduces several proposals for improvement. As an emerging market, analysis starts by examining available and ratified network standards suitable for low power applications. After identifying the IEEE 802.15.4 standard (commercially known as ZigBee) as the one of choice, and analysing several front-end architectures on which its transceiver circuitry can be based, an application, the Tyre Pressure Monitoring System (TPMS) is selected to examine the capabilities of the standard and its most suitable architecture in satisfying the application’s requirements. From this compatibility analysis, the most significant shortcomings are identified as interference and power consumption. The work presented in this thesis focuses on the power consumption issues. A comparison of available high frequency transistor technologies concludes Silicon CMOS to be the most appropriate solution for the implementation of low cost and low power ZigBee transceivers. Since the output power requirement of ZigBee is relatively modest, it is possible to consider the design of a single amplifier block which can act as both a Low Noise Amplifier (LNA) in the receiver chain and a Power Amplifier (PA) on the transmitter side. This work shows that by employing a suitable design methodology, a single dual-function amplifier can be realised which meets the required performance specification. In this way, power consumption and chip area can both be reduced, leading to cost savings so vital to the widespread utilisation of the ZigBee standard. Given the importance of device nonlinearity in such a design, a new transistor model based on independent representation of each of the transistor’s nonlinear elements is developed with the aim of quantifying the individual contribution of each of the transistors nonlinear elements, to the total distortion. The methodology to the design of the dual functionality (LNA/PA) amplifier starts by considering various low noise amplifier architectures and comparing them in terms of the trade-off between noise (required for LNA operation) and linearity (important for PA operation), and then examining the behaviour of the selected architecture (the common-source common-gate cascode) at higher than usual input powers. Due to the need to meet the far apart performance requirements of both the LNA and PA, a unique amplifier design methodology is developed The design methodology is based on simultaneous graphical visualisation of the relationship between all relevant performance parameters and corresponding design parameters. A design example is then presented to demonstrate the effectiveness of the methodology and the quality of trade-offs it allows the designer to make. The simulated performance of the final amplifier satisfies both the requirements of ZigBee’s low noise and power amplification. At 2.4GHz, the amplifier is predicted to have 1.6dB Noise Figure (NF), 6dBm Input-referred 3rd-order Intercept Point (IIP3), and 1dB compression point of -3.5dBm. In low power operation, it is predicted to have 10dB gain, consuming only 8mW. At the higher input power of 0dBm, it is predicted to achieve 24% Power-Added Efficiency (PAE) with 8dB gain and 22mW power consumption. Finally, this thesis presents a set of future research proposals based on problems identified throughout its development

A flicker noise/IM3 cancellation technique for active mixer using negative impedance

This paper presents an approach to simultaneously cancel flicker noise and IM3 in Gilbert-type mixers, utilizing negative impedances. For proof of concept, two prototype double-balanced mixers in 0.16- m CMOS are fabricated. The first demonstration mixer chip was optimized for full IM3 cancellation and partial flicker noise cancellation; this chip achieves 9-dB flicker noise suppression, improvements of 10 dB for IIP3, 5 dB for conversion gain, and 1 dB for input P1 dB while the thermal noise increased by 0.1 dB. The negative impedance increases the power consumption for the mixer by 16% and increases the die area by 8% (46 28 m ). A second demonstration mixer chip aims at full flicker noise cancellation and partial IM3 cancellation, while operating on a low supply voltage ( 0.67 x Vdd; in this chip,the negative impedance increases the power consumption by 7.3% and increases the die area by 7% (50 20 m ). For one chip sample, measurements show 10-dB flicker noise suppression within 200% variation of the negative impedance bias current; for ten randomly selected chip samples, 11-dB flicker noise suppression is measured

Frequency Translation loops for RF filtering-Theory and Design

Modern wireless transceivers are required to operate over a wide range of frequencies in order to support the multitude of currently available wireless standards. Wideband operation also enables future systems that aim for better utilization of the available spectrum through dynamic allocation. As such, co-existence problems like harmonic mixing and phase noise become a main concern. In particular, dealing with interfer- ence scenarios is crucial since they directly translate to higher linearity requirements in a receiver. With CMOS driving the consumer electronics market due to low cost and high level of integration demands, the continued increase in speed, mainly intended for digital applications, oers new possibilities for RF design to improve the linearity of front-end receivers. Furthermore, the readily available switches in CMOS have proven to be a viable alternative to traditional active mixers for frequency translation due to their high linearity, low flicker noise, and, most recently recognized, their impedance transformation properties. In this thesis, frequency translation feedback loops employing passive mixers are explored as a means to relax the linearity requirements in a front-end receiver by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture employing such loop addresses some of the most common prob- lems of integrated RF lters, while maintaining their inherent tunability. Through a simplied and intuitive analysis, the operation of the receiver is first examined and the design parameters aecting the lter characteristics, such as band- width and stop-band rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-o between noise, linearity and harmonic radiation. Next, a detailed analysis of frequency translation loops using passive mixers is developed. Only highly simplied analysis of such loops is commonly available in literature. The analysis is based on an iterative procedure to address the complexity introduced by the presence of LO harmonics in the loop and the lack of reverse isolation in the mixers, and results in highly accurate expressions for the harmonic and noise transfer functions of the system. Compared to the alternative of applying general LPTV theory, the procedure developed oers more intuition into the operation of the system and only requires the knowledge of basic Fourier analysis. The solution is shown to be capable of predicting trade-os arising due to harmonic mixing and loop stability requirements, and is therefore useful for both system design and optimization. Finally, as a proof of concept, a chip prototype is designed in a standard 65nm CMOS process. The design occupies +12dBm. As such, the work presented in this thesis aims to provide a highly-integrated means for programmable RF channel selection in wideband receivers. The topic oers several possibilities for further research, either in terms of extending the viability of the system, for example by providing higher order ltering, or by improving performance, such as noise

An RF System Design for an Ultra Wideband Indoor Positioning System

Three main elements for an indoor positioning and navigation system design are the signal structure, the signal processing algorithm and the digital and RF prototype hardware. This thesis focuses on the design and development of RF prototype hardware. The signal structure being used in the precise positioning system discussed in this thesis is a Multicarrier-Ultra Wideband (MC-UWB) type signal structure. Unavailability of RF modules suitable for MC-UWB based systems, led to design and development of custom RF transmitter and receiver modules which can be used for extensive field testing. The lack of RF design guidelines for multicarrier positioning systems that operate over fractional bandwidth ranging from 10% to 25% makes the RF design challenging as the RF components are stressed using multicarrier signal in a way not anticipated by the designers. This thesis, first presents simulation based performance evaluation of impulse radio based and multicarrier based indoor positioning systems. This led to an important revelation that multicarrier based positioning system is preferred over impulse radio based positioning systems. Following this, ADS simulations for a direct upconversion transmitter and a direct downconversion receiver, using multicarrier signal structure is presented. The thesis will then discuss the design and performance of the 24% fractional bandwidth RF prototype transmitter and receiver custom modules. This optimized 24% fractional bandwidth RF design, under controlled testing environment demonstrates positioning accuracy improvement by 2-4 times over the initial 11% fractional bandwidth non-optimized RF design. The thesis will then present the results of various indoor wireless tests using the optimized RF prototype modules which led to better understanding of the issues in a field deployable indoor positioning system

Integrated Self-Interference Cancellation for Full-Duplex and Frequency-Division Duplexing Wireless Communication Systems

From wirelessly connected robots to car-to-car communications, and to smart cities, almost every aspect of our lives will benefit from future wireless communications. While promise an exciting future world, next-generation wireless communications impose requirements on the data rate, spectral efficiency, and latency (among others) that are higher than those for today's systems by several orders of magnitude. Full-duplex wireless, an emergent wireless communications paradigm, breaks the long-held assumption that it is impossible for a wireless device to transmit and receive simultaneously at the same frequency, and has the potential to immediately double network capacity at the physical (PHY) layer and offers many other benefits (such as reduced latency) at the higher layers. Recently, discrete-component-based demonstrations have established the feasibility of full-duplex wireless. However, the realization of integrated full duplex radios, compact radios that can fit into smartphones, is fraught with fundamental challenges. In addition, to unleash the full potential of full-duplex communication, a careful redesign of the PHY layer and the medium access control (MAC) layer using a cross-layer approach is required. The biggest challenge associated with full duplex wireless is the tremendous amount of transmitter self-interference right on top of the desired signal. In this dissertation, new self-interference-cancellation approaches at both system and circuit levels are presented, contributing towards the realization of full-duplex radios using integrated circuit technology. Specifically, these new approaches involve elimination of the noise and distortion of the cancellation circuitry, enhancing the integrated cancellation bandwidth, and performing joint radio frequency, analog, and digital cancellation to achieve cancellation with nearly one part-per-billion accuracy. In collaboration with researchers at higher layers of the stack, a cross-layer approach has been used in our full-duplex research and has allowed us to derive power allocation algorithms and to characterize rate-gain improvements for full-duplex wireless networks. To enable experimental characterization of full-duplex MAC layer algorithms, a cross-layered software-defined full-duplex radio testbed has been developed. In collaboration with researchers from the field of micro-electro-mechanical systems, we demonstrate a multi-band frequency-division duplexing system using a cavity-filter-based tunable duplexer and our integrated widely-tunable self-interference-cancelling receiver

Architectures, Antennas and Circuits for Millimeter-wave Wireless Full-Duplex Applications

Demand for wireless network capacity keeps growing exponentially every year, as a result a 1000-fold increase in data traffic is projected over the next 10 years in the context of 5G wireless networks. Solutions for delivering the 1000-fold increase in capacity fall into three main categories: deploying smaller cells, allocating more spectrum and improving spectral efficiency of wireless systems. Smaller cells at RF frequencies (1-6GHz) are unlikely to deliver the demanded capacity increase. On the other hand, millimeter-wave spectrum (frequencies over 24GHz) offers wider, multi-GHz channel bandwidths, and therefore has gained significant research interest as one of the most promising solutions to address the data traffic demands of 5G. Another disruptive technology is full-duplex which breaks a century-old assumption in wireless communication, by simultaneous transmission and reception on the same frequency channel. In doing so, full-duplex offers many benefits for wireless networks, including an immediate spectral efficiency improvement in the physical layer. Although FD promises great benefits, self-interference from the transmitter to its own receiver poses a fundamental challenge. The self-interference can be more than a billion times stronger than the desired signal and must be suppressed below the receiver noise floor. In recent years, there has been some research efforts on fully-integrated full-duplex RF transceivers, but mm-wave fully-integrated full-duplex systems, are still in their infancy. This dissertation presents novel architectures, antenna and circuit techniques to merge two exciting technologies, mm-wave and full-duplex, which can potentially offer the dual benefits of wide bandwidths and improved spectral efficiency. To this end, two different antenna interfaces, namely a wideband reconfigurable T/R antenna pair with polarization-based antenna cancellation and an mm-wave fully-integrated magnetic-free non-reciprocal circulator, are presented. The polarization-based antenna cancellation is employed in conjunction with the RF and digital cancellation to design a 60GHz full-duplex 45nm SOI CMOS transceiver with nearly 80dB self-interference suppression. The concepts and prototypes presented in this dissertation have also profound implications for emerging applications such as vehicular radars, 5G small-cell base-stations and virtual reality

Feedback methods for inductorless bandwidth extension and linearisation of post-amplifiers in optical receiver frontends

Optical communication is increasingly important in today's telecommunications. It is not only a key component in long-haul infrastructure, but is also being brought into new applications within the datacentre, at the circuit board and integrated circuit level, and in next generation mobile networks. This thesis proposes feedback tuning approaches in order to address two challenges within optical receiver analog frontend circuits: a) the dynamic response of a prior bandwidth extension technique; and b) linearity optimisation. To address dynamic response, we begin with an inductorless method of bandwidth extension using positive feedback loops. In a multi-stage post-amplifier with local positive feedback loops, we propose an approach which tunes each positive feedback gain separately, and demonstrate that this achieves better dynamic response and eye opening than the prior equal-feedback-gain approach. We additionally propose root-locus analysis as a means of characterising dynamic response, and suggest some design guidelines based on this analysis. To address linearity optimisation, we propose the use of an interleaving negative-feedback post-amplifier topology, previously proposed only for bandwidth extension. We investigate the relationship between the feedback gains and linearity and develop a design approach for linearity optimisation. We then designed and fabricated two 70 dB 6 GHz optical receiver circuits, making use of two different post-amplifiers, in order to compare different design approaches. We achieved a linearity of 0.08 dBVrms OIP3 (quasi-static) and a THD of 0.195\% at 1 GHz

DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems