On-line Testing Field Programmable Analog Array Circuits

This work presents an efficient methodology to on-line test field programmable analog array (FPAA) circuits. It proposes to partition the FPAA circuit under test into sub circuits. Each sub circuit is tested by replicating the sub circuit with programmable resources on FPAAs, and comparing the outputs of the original partitioned sub circuit and its replication. The advantages of this approach includes: low implementation cost, enhanced testability, and flexible testing schedules. This work also presents circuit techniques to address stability problems which are often encountered in the proposed on-line testing approach. In addition, the impact of performing circuit partition on testability is investigated in this work. It shows that testability is generally improved in partitioned circuits. Finally, experimental results are presented to demonstrate the feasibility and effectiveness of the proposed techniques

An analog checker with inputrelative tolerance for duplicate signals

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Analog checkers with absolute and relative tolerances

The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code fails out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattern generator for off-line testing of the checkers is proposed

Analog checkers with absolute and relative tolerances

ISSN: 0278-0070The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code fails out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattern generator for off-line testing of the checkers is proposed