Implementation and Design of SHA-1 Algorithm

The substantive technologies are having so plenty algorithms for crypto systems. All the technologies are famous for message authentication or message compression techniques like DSA, RSA and SHA-1.These are majorly streamed on compressed techniques only not on Authentication Requirements like Masquerade, Content Modification, Sequence Modification and Timing Modification. However the previous SHA-1 failure using brute force attack in 280 operations and Collision failure found in 2005 in 233 operations. So we address the above problem and focused on SHA-2 cryptography algorithms

High Speed and Throughput Evaluation of SHA-1 Hash Function Design with Pipelining and Unfolding Transformation Techniques

In recent years, designing of SHA-1 hash function has become popular because it was important in security design application. One of the applications of SHA-1 hash function was HMAC where the architecture of SHA-1 needed to be improved in terms of speed and throughput in order to obtain the highperformance design. The objective of this project was to design high speed and throughput evaluation of SHA-1 hash function based on a combination of pipelining and unfolding techniques. By using both techniques in designing the architecture of SHA- 1 design, the speed of SHA-1 hash function can be increased significantly as well as throughput of the design. In this paper, five proposed SHA-1 architectures were designed with different stages of pipelining such as 1, 4 and 40 stages. The results showed the high-speed design of SHA-1 design can be obtained by using 40 stages pipelining with unfolding factor two. This design provided a high-speed implementation with maximum frequency of 308.17 MHz on Arria II GX and 458.59 MHz on Virtex 5 XC5VLX50T. Furthermore, the throughput of the design also increased about 150.269 Gbps and 223.618 Gbps on Arria II GX and Virtex 5 XC5VLX50T respectively. Thus, highspeed design of SHA-1 hash function was successfully obtained which can give benefit to society especially in security system data transmission and other types of hash functions

High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs

Secure hash algorithms (SHAs) are important components of cryptographic applications. SHA performance on central processing units (CPUs) is slow, therefore, acceleration must be done using hardware such as Field Programmable Gate Arrays (FPGAs). Considerable work has been done in academia using FPGAs to accelerate SHAs. These designs were implemented using Hardware Description Language (HDL) based design methodologies, which are tedious and time consuming. High Level Synthesis (HLS) enables designers to synthesize optimized FPGA hardware from algorithm specifications in programming languages such as C/C++. This substantially reduces the design cost and time. In this thesis, the Altera SDK for OpenCL (AOCL) HLS tool was used to synthesize the SHAs on FPGAs and to explore the design space of the algorithms. The results were evaluated against the previous HDL based designs. Synthesized FPGA hardware performance was comparable to the HDL based designs despite the simpler and faster design process