Robust Digital Predistortion in Saturation Region of Power Amplifiers

This paper proposes a digital predistortion (DPD) technique to improve linearization performance when the power amplifier (PA) is driven near the saturation region. The PA is a non-linear device in general, and the nonlinear distortion becomes severer as the output power increases. However, the PA’s power efficiency increases as the PA output power increases. The nonlinearity results in spectral regrowth, which leads to adjacent channel interference, and degrades the transmit signal quality. According to our simulation, the linearization performance of DPD is degraded abruptly when the PA operates in its saturation region. To relieve this problem, we propose an improved DPD technique. The proposed technique performs on/off control of the adaptive algorithm based on the magnitude of the transmitted signal. Specifically, the adaptation normally works for small and medium signals while it stops for large signals. Therefore, harmful coefficient updates by saturated signals can be avoided. A computer simulation shows that the proposed method can improve the linearization performance compared with the conventional DPD method in highly driven PAs

Equalization-Based Digital Background Calibration Technique for Pipelined ADCs

In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC

A Digital Predistortion Scheme Exploiting Degrees-of-Freedom for Massive MIMO Systems

The primary source of nonlinear distortion in wireless transmitters is the power amplifier (PA). Conventional digital predistortion (DPD) schemes use high-order polynomials to accurately approximate and compensate for the nonlinearity of the PA. This is not practical for scaling to tens or hundreds of PAs in massive multiple-input multiple-output (MIMO) systems. There is more than one candidate precoding matrix in a massive MIMO system because of the excess degrees-of-freedom (DoFs), and each precoding matrix requires a different DPD polynomial order to compensate for the PA nonlinearity. This paper proposes a low-order DPD method achieved by exploiting massive DoFs of next-generation front ends. We propose a novel indirect learning structure which adapts the channel and PA distortion iteratively by cascading adaptive zero forcing precoding and DPD. Our solution uses a 3rd order polynomial to achieve the same performance as the conventional DPD using an 11th order polynomial for a 100x10 massive MIMO configuration. Experimental results show a 70% reduction in computational complexity, enabling ultra-low latency communications.Comment: IEEE International Conference on Communications 201

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Closed-Loop Control of a Piezo-Fluidic Amplifier

Fluidic valves based on the Coand\u{a} effect are increasingly being considered for use in aerodynamic flow control applications. A limiting factor is their variation in switching time, which often precludes their use. The purpose of this paper is to demonstrate the closed-loop control of a recently developed, novel piezo-fluidic valve that reduces response time uncertainty at the expense of operating bandwidth. Use is made of the fact that a fluidic jet responds to a piezo tone by deflecting away from its steady state position. A control signal used to vary this deflection is amplitude modulated onto the piezo tone. Using only a pressure measurement from one of the device output channels, an output-based LQG regulator was designed to follow a desired reference deflection, achieving control of a 90 m/s jet. Finally, the controller's performance in terms of disturbance rejection and response time predictability is demonstrated.Comment: 31 pages, 23 figures. Published in AIAA Journal, 4th May 202

Adaptive digital predistortion for linearization of power amplifier

Ankara : The Department of Electrical and electronics Engineering and the Institute of Engineering and Science of Bilkent University, 2009.Thesis (Master's) -- Bilkent University, 2009.Includes bibliographical references leaves 55.In most communication systems, power amplifiers are used to obtain high output power. The nonlinear characteristics of the power amplifier leads to the distortion of the output signal. This distortion affects the efficiency of the power amplifier. The way to reduce this effect is to linearize the power amplifier near the saturation region where it is nonlinear. The widely used technique for the linearization of power amplifiers is predistortion. The proposed technique for predistortion uses a LUT(look-up-table), a complex multiplier, an address calculator, delay elements and an adaptation logic. A new adaptation logic to update the LUT coefficients, is used. The predistorter is simulated in Matlab software using a baseband model for the power amplifier. 16-QAM baseband modulation is used to simulate the predistorter. In order to see the performance of the proposed predistorter, hardware logic is implemented in FPGA and experimental setup with RF circuits and RF power amplifier is used. For different LUT sizes, the algorithm is tested and for the LUT size of 64, nearly 15 dB improvement in power spectrum is observed. The LUT size of 64 is observed to be the optimal LUT size in the experiments.Şekerlisoy, BurakM.S

High frequency CMOS amplifier with improved linearity

In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which is appropriate for RF/microwave applications. A single-chip CMOS amplifier has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD3 improved by 14 dB, OIP3 improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved

Improved method for SNR prediction in machine-learning-based test

This paper applies an improved method for testing the signal-to-noise ratio (SNR) of Analogue-to-Digital Converters (ADC). In previous work, a noisy and nonlinear pulse signal is exploited as the input stimulus to obtain the signature results of ADC. By applying a machine-learning-based approach, the dynamic parameters can be predicted by using the signature results. However, it can only estimate the SNR accurately within a certain range. In order to overcome this limitation, an improved method based on work is applied in this work. It is validated on the Labview model of a 12-bit 80 Ms/s pipelined ADC with a pulse- wave input signal of 3 LSB noise and 7-bit nonlinear rising and falling edges