Temperature Estimation of SiC Power Devices Using High Frequency Chirp Signals

Silicon carbide devices have become increasingly popular in electric vehicles, predominantly due to their fast-switching speeds, which allow for the construction of smaller power converters. Temperature sensitive electrical parameters (TSEPs) can be used to determine the junction temperature, just like silicon-based power switches. This paper presents a new technique to estimate the junction temperature of a single-chip silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET). During off-state operation, high-frequency chirp signals below the resonance frequency of the gate-source impedance are injected into the gate of a discrete SiC device. The gate-source voltage frequency response is captured and then processed using the fast Fourier transform. The data is then accumulated and displayed over the chirp frequency spectrum. Results show a linear relationship between the processed gate-source voltage and the junction temperature. The effectiveness of the proposed TSEPs is demonstrated in a laboratory scenario, where chirp signals are injected in a stand-alone biased discrete SiC module, and in an in-field scenario, where the TSEP concept is applied to a MOSFET operating in a DC/DC converter

Temperature sensitive electrical parameters for condition monitoring in SiC power MOSFETs

This paper presents an analysis of the turn ON transient for SiC power MOSFETs and defines a Temperature Sensitive Electrical Parameter (TSEP) which is suitable for condition monitoring. The drain current switching rate dIDS/dt and its temperature dependency have been measured and analysed for commercially available 1.2 kV/10 A, 1.2 kV/24 A and 1.2 kV/42 A SiC MOSFETs from Wolfspeed showing that at lower switching speeds, i.e. using high gate resistances, it can be a suitable TSEP for condition monitoring. The impact of temperature on the switching speed indicates that the current switching rate is a more effective TSEP for higher current rated devices and the evaluation of the switching losses suggests that the sacrifice in switching speed for enabling the ability of estimating the junction temperature is not a major trade-off

A novel non-intrusive technique for BTI characterization in SiC MOSFETs

Threshold voltage ( $V_{TH}$ ) shift due to Bias Temperature Instability (BTI) is a well-known problem in SiC-MOSFETs that occurs due to oxide traps in the $SiC/SiO_2$ gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC-MOSFETs makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which $V_{TH}$ shift is monitored. However, some recovery occurs between the end of the stress and $V_{TH}$ characterisation, thereby potentially under-estimating the extent of the problem. In applications where the SiC-MOSFET is turned OFF with a negative bias at high temperature, if $V_{TH}$ shift is severe enough there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn-ON. In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring $V_{TH}$ shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar SiC-MOSFETs due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess $V_{TH}$ shift dynamically during BTI characterization tests

Compact electrothermal reliability modeling and experimental characterization of bipolar latchup in SiC and CoolMOS power MOSFETs

In this paper, a compact dynamic and fully coupled electrothermal model for parasitic BJT latchup is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latchup can be triggered by body-diode reverse-recovery hard commutation with high dV/dt or from avalanche conduction during unclamped inductive switching. In the case of body-diode reverse recovery, the base current that initiates BJT latchup is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the antiparallel p-i-n body diode. For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latchup, whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latchup during reverse recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of benchmarking the robustness of power MOSFETs