Further Parameters Estimation of Neocognitron Neural Network Modification with FFT Convolution

This paper presents further development of an improved version of the neocognitron algorithm introduced by Fukushima. Some comparisons of other symbol recognition methods based on the neocognitron neural network are also performed, which led to the proposal of several modifications — namely, layer dimension adjustment, threshold function and connection Gaussian kernel estimation. The width and height are taken into account independently in order to improve the recognition of patterns of slightly different dimensions. The learning and recognition calculations are performed as FFT convolutions in order to utilize external specialized computing system. Finally, more detailed results of the neocognitron performance evaluation are provided

Support Vector Machine Histogram: New Analysis and Architecture Design Method of Deep Convolutional Neural Network

Deep convolutional neural network (DCNN) is a kind of hierarchical neural network models and attracts attention in recent years since it has shown high classification performance. DCNN can acquire the feature representation which is a parameter indicating the feature of the input by learning. However, its internal analysis and the design of the network architecture have many unclear points and it cannot be said that it has been sufficiently elucidated. We propose the novel DCNN analysis method “Support vector machine (SVM) histogram” as a prescription to deal with these problems. This is a method that examines the spatial distribution of DCNN extracted feature representation by using the decision boundary of linear SVM. We show that we can interpret DCNN hierarchical processing using this method. In addition, by using the result of SVM histogram, DCNN architecture design becomes possible. In this study, we designed the architecture of the application to large scale natural image dataset. In the result, we succeeded in showing higher accuracy than the original DCNN

Feature extraction using neocognitron learning in hierarchical temporary memory

Hierarchical Temporal Memory (HTM) serves as a practical implementation of the memory prediction theory.In order to obtain the optimum accuracy in pattern recognition, it is crucial to apply an appropriate learning algorithm for the feature extraction step of the HTM.This study proposes the use of neocognitron learning in extracting features of the pattern for image recognition.The integration of neocognitron into HTM addresses both the scale and time issues of the HTM. As for evaluation, a comparison is made against the original HTM and principal component analysis (PCA).The results show that more features are extracted as a function of input patterns than the original HTM and PCA

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16x16 has been implemented with programmable kernel size of up to 16x16. The chip has been fabricated in a standard 0.35- m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.Commission of the European Communities IST-2001-34124 (CAVIAR)Commission of the European Communities 216777 (NABAB)Ministerio de Educación y Ciencia TIC-2000-0406-P4Ministerio de Educación y Ciencia TIC-2003-08164-C03-01Ministerio de Educación y Ciencia TEC2006-11730-C03-01Junta de Andalucía TIC-141