Optimization of multilayer micro channels heat sinks cooling system using genetic algorithm

Cooling of electronic devices is problematic by its nature simply because of the space restriction. Recent advances in high powered miniaturized electronic systems have come at the expanse of very high heat fluxes that pose challenges to thermal management research. Uncontrolled excessive heat may cause thermal fatigue and stresses and the current micro electro-mechanical cooling systems (MEMS) which utilize the single layer micro channel heat sink, introduced a decade ago, may no longer be an adequate solution. Possible extension of the layer of parallel micro channels into a stacked system, by developing two, three, and multi-layer channel systems are being investigated. The design of all these systems depends on several parameters; coolant type, channel geometry, channel dimensions, and the number of the channels. This paper reports a new model for optimizing the thermal resistance, developed based on specific parameters of the dimensions of the channel, the wall width between the channels, and using water as a coolant at 27°C. The outcomes of the model were compared with other published studies. The results showed that the model is valid and reliable for further studies

Functional optimization of a Persian lime packing using TRIZ and multi-objective genetic algorithms

This article proposes a novel approach that uses a mathematical model optimized by Genetic Algorithms harmonized with the Russian theory of problem solving and invention (TRIZ) to design an export packing of Persian Lime. The mathematical model (with functional elements of non-spatial type) optimizes the spaces of the Persian Lime Packing, maximizes the Resistance to Vertical Compression and minimizes the Amount of Material Used, according to the operation restrictions of the packing during the transport of the merchandise. This approach is developed in four phases: the identification of the solution space; the optimization of the conceptual design; the application of TRIZ; and the generation of the final proposal solution. The results show the proposed packing (with 28% less cardboard) supports at least the same vertical load with respect to the nearest competitor packing. However, with the same number of packings per pallet and pallets per container, the space used by the packing assembled and deployed in the container is greater by 10% and 38% respectively. Besides, TRIZ includes innovative non-spatial elements such as the airflow and the friction of the product inside the packing. The contribution of this approach can be replicable for the packing design of other horticultural products of the agri-food chai

Parametric and design analysis on thermoelectric generators

In facing the limited energy source reserves and environmental problems, thermoelectric generators (TEGs) are one of the promising waste heat recovery systems. The modern TEGs for exhaust stream (e.g. from automobiles) can improve the fuel economy by around 5%, taking advantage of the recent developed thermoelectric (TE) materials. In this work, we aimed at designing a TEG as an add-on module for a gas-phase heat exchanger with maximized power output, and without negative impact (e.g. maintaining a minimum heat dissipation rate from the hot side). We first developed a parametric optimization algorithm using response surface method (RSM) and genetic algorithm (GA) for the numerical model. The numerical model handles varied types of heat exchangers (cross flow and counter flow) with the finite volume method and calculates the thermoelectric modules (TEMs) with thermal resistance network analyses. TEMs based on filled-skutterudite and bismuth telluride are used respectively in higher and lower temperature regions. The RSM results also provide knowledge on sensitivity and interaction of parameters. The combined RSM-GA optimization algorithm will be generally useful for the parametric design of TEGs, especially before much knowledge acquired on the TEG parameters. The regenerative concept for TEG (R-TEG) is then introduced. Instead of developing advanced high figure-of-merit (ZT) high-temperature TE materials, we use a gas phase heat exchanger (precooler) to lower the temperature of the hot gas and at the same time regenerate hot air from the cold air supply for Bi2Te3-based TEGs, avoiding the use of high-temperature thermoelectric materials. It is found that the regenerative TEGs can achieve a similar power output compared with TEGs using high-temperature TE materials such as filled-skutterudites (combined filled-skutterudites and Bi2Te 3-based TE materials), by obtaining a higher heat scavenging rate. Thus, the regenerative TEGs also show a similar absolute efficiency, defined according to the total available enthalpy from the hot gas. This could represent a paradigm shift in the TEG research and development, that much lower-cost, reliable, and readily available Bi2Te3-based materials and modules can be used for high-temperature applications, and will ultimately enable the widespread deployment of TEGs for real world waste heat recovery applications. Lastly, a single module TEG is developed experimentally for both characterization of TEMs and low-cost diagnoses of component performance inside TEGs. A commercialized Bi2Te3-based module is tested. Temperatures along the streams and across the TEM packaging are investigated. A better-defined single module TEG with internal detailed information available can be used as a reduced size experimental model to validate the numerical result

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

Heurísticas bioinspiradas para el problema de Floorplanning 3D térmico de dispositivos MPSoCs

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 20-06-2013Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu