Wafer level reliability for high-performance VLSI design

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Commercial Off-The-Shelf (COTS) Parts Risk and Reliability User and Application Guide

All COTS parts are not created equal. Because they are not created equal, the notion that one can force the commercial industry to follow a set of military specifications and standards, along with the certifications, audits and qualification commitments that go with them, is unrealistic for the sale of a few parts. The part technologies that are Defense Logistics Agency (DLA) certified or Military Specification (MS) qualified, are several generations behind the state-of-the-art high-performance parts that are required for the compact, higher performing systems for the next generation of spacecraft and instruments. The majority of the part suppliers are focused on the portion of the market that is producing high-tech commercial products and systems. To that end, in order to compete in the high performance and leading edge advanced technological systems, an alternative approach to risk assessment and reliability prediction must be considered

Nonphotolithographic nanoscale memory density prospects

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations

Effects of cosmic rays on single event upsets

The efforts at establishing a research program in space radiation effects are discussed. The research program has served as the basis for training several graduate students in an area of research that is of importance to NASA. In addition, technical support was provided for the Single Event Facility Group at Brookhaven National Laboratory

Manipulating nanoscale structure to control functionality in printed organic photovoltaic, transistor and bioelectronic devices.

Printed electronics is simultaneously one of the most intensely studied emerging research areas in science and technology and one of the fastest growing commercial markets in the world today. For the past decade the potential for organic electronic (OE) materials to revolutionize this printed electronics space has been widely promoted. Such conviction in the potential of these carbon-based semiconducting materials arises from their ability to be dissolved in solution, and thus the exciting possibility of simply printing a range of multifunctional devices onto flexible substrates at high speeds for very low cost using standard roll-to-roll printing techniques. However, the transition from promising laboratory innovations to large scale prototypes requires precise control of nanoscale material and device structure across large areas during printing fabrication. Maintaining this nanoscale material control during printing presents a significant new challenge that demands the coupling of OE materials and devices with clever nanoscience fabrication approaches that are adapted to the limited thermodynamic levers available. In this review we present an update on the strategies and capabilities that are required in order to manipulate the nanoscale structure of large area printed organic photovoltaic (OPV), transistor and bioelectronics devices in order to control their device functionality. This discussion covers a range of efforts to manipulate the electroactive ink materials and their nanostructured assembly into devices, and also device processing strategies to tune the nanoscale material properties and assembly routes through printing fabrication. The review finishes by highlighting progress in printed OE devices that provide a feedback loop between laboratory nanoscience innovations and their feasibility in adapting to large scale printing fabrication. The ability to control material properties on the nanoscale whilst simultaneously printing functional devices on the square metre scale is prompting innovative developments in the targeted nanoscience required for OPV, transistor and biofunctional devices

Yield and Reliability Analysis for Nanoelectronics

As technology has continued to advance and more break-through emerge, semiconductor devices with dimensions in nanometers have entered into all spheres of our lives. Accordingly, high reliability and high yield are very much a central concern to guarantee the advancement and utilization of nanoelectronic products. However, there appear to be some major challenges related to nanoelectronics in regard to the field of reliability: identification of the failure mechanisms, enhancement of the low yields of nano products, and management of the scarcity and secrecy of available data [34]. Therefore, this dissertation investigates four issues related to the yield and reliability of nanoelectronics. Yield and reliability of nanoelectronics are affected by defects generated in the manufacturing processes. An automatic method using model-based clustering has been developed to detect the defect clusters and identify their patterns where the distribution of the clustered defects is modeled by a new mixture distribution of multivariate normal distributions and principal curves. The new mixture model is capable of modeling defect clusters with amorphous, curvilinear, and linear patterns. We evaluate the proposed method using both simulated and experimental data and promising results have been obtained. Yield is one of the most important performance indexes for measuring the success of nano fabrication and manufacturing. Accurate yield estimation and prediction is essential for evaluating productivity and estimating production cost. This research studies advanced yield modeling approaches which consider the spatial variations of defects or defect counts. Results from real wafer map data show that the new yield models provide significant improvement in yield estimation compared to the traditional Poisson model and negative binomial model. The ultra-thin SiO2 is a major factor limiting the scaling of semiconductor devices. High-k gate dielectric materials such as HfO2 will replace SiO2 in future generations of MOS devices. This study investigates the two-step breakdown mechanisms and breakdown sequences of double-layered high-k gate stacks by monitoring the relaxation of the dielectric films. The hazard rate is a widely used metric for measuring the reliability of electronic products. This dissertation studies the hazard rate function of gate dielectrics breakdown. A physically feasible failure time distribution is used to model the time-to-breakdown data and a Bayesian approach is adopted in the statistical analysis

On the Electro‐Optics of Carbon Stack Perovskite Solar Cells

Mesoporous carbon stack architecture is attracting considerable interest as a candidate for scalable, low‐cost perovskite solar cells amenable to high‐throughput manufacturing. These cells are characterized by microns‐thick mesoporous titania and zirconia layers capped by a nonselective carbon electrode with the whole stack being infused with a perovskite semiconductor. Although the architecture does not deliver the >20% power conversion efficiencies characteristic of perovskite planar and mesoporous geometries, it does produce cells with respectable efficiencies >16%, which is unexpected due to the carbon electrode being a nonideal anode and the active layers being so thick. Optimization of these cells requires an understanding of the coupled efficiencies of light absorption, charge generation, and extraction which is currently unavailable. Herein, a combined experimental‐simulation study that elucidates photogeneration and extraction is reported. By determining the optical constants of the individual components and using effective‐medium approximations, the internal quantum efficiencies (IQE) in both the titania and zirconia layers are determined to be ≈85%. Numerical drift‐diffusion simulations indicate that this high IQE is a consequence of the thick junctions reducing minority carrier concentrations at the electrodes, thereby decreasing surface recombination. This insight can now be used to tune the carbon stack for efficiency and simplicity