Phase coding of RF pulses in photonics-aided frequency-agile coherent radar systems

An innovative optical scheme to generate software-defined phase-modulated radio frequency (RF) pulses with carrier frequency agility from a mode-locked laser (MLL) is proposed. The technique exploits a direct digital synthesizer and a Mach-Zehnder modulator to apply an intermediate frequency modulation to the MLL's modes. The heterodyne detection of the optical signal allows the generation of amplitude- and phase-modulated RF carriers with very high phase stability, suitable for coherent radar applications. Further, a single MLL can be used to generate carriers simultaneously at different frequencies, enabling frequency hopping or multifunctional radars, with no need to increase the complexity of the transmitter. Results show chirped and Barker-coded pulses at around 10 or 40 GHz in a single setup, without any performance degradation while increasing the carrier frequency. The proposed technique allows the practical realization of compressed pulses for coherent radars over a wide carrier frequency range, allowing the development of software-defined radar systems with improved functionalities. © 1965-2012 IEEE

Reduction of acoustic feedback oscillations by use of spectrum shifting

The problem of whistling noise or self-oscillation in public address systems operating in closed halls or rooms can be very disturbing to the listeners. This noise is sustained when the positive acoustic feedback, of the public address-room system, meets the oscillation criteria. This feedback system results from the acoustic sound signal reflected off the room walls and any other obstacles in the room, originating from the public address speakers and then re-entering the microphone. When all of the audio signal components entering the public address system are shifted by a frequency increment Δf of 6 Hz, an increase of 5 dB in the useable signal level was achieved and whistling noise reduction is attained. This thesis describes an apparatus for frequency shifting by small increments in steps of 1 Hz. The system is of simple implementation and effectively reduces the whistling noise and increases the value of achievable gain without introducing any speech distortions. While the idea turned out to be not original, since it was described in the early sixties, the time for it may be now, because integrated circuits made it feasible in terms of cost, size and portability. Due to this, we feel that reintroducing the idea at this time may be fortuitous

Design of high performance frequency synthesizers in communication systems

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Photonic Technologies for Radar and Telecomunications Systems

The growing interest in flexible architectures radio and the recent progress in the high speed digital signal processor make a software defined radio system an enabling technology for several digital signals processing architecture and for the flexible signal generation. In this direction wireless radar\telecommunications receiver with digital backend as close as possible to the antenna, as well as the software defined signal generation, reaches several benefits in term of reconfigurabilty, reliability and cost with respect to the analogical front-ends. Unfortunately the present scenario ensures direct sampling and digital downconversion only at the intermediate frequency. Therefore these kinds of systems are quite vulnerable to mismatches and hardware non-idealities in particular due to the mixers stages and filtering process. Furthermore, since the limited input bandwidth, speed and precision of the analog to digital converters represent the main digital system‘s bottleneck, today‘s direct radio frequency sampling is only possible at low frequency. On the other hand software defined signals can be generated exploiting direct digital synthesizers followed by an up-conversion to the desired carrier frequency. State-of-the-art synthesizers (limited to few GHz) introduce quantization errors due to digital-to-analog conversion, and phase errors depending on the phase stability of their internal clock. In addition the high phase stability required in modern wireless systems (such as radar systems) is becoming challenging for the electronic RF signal generation, since at high carrier frequency the frequency multiplication processes that are usually exploited reduce the phase stability of the original RF oscillators. Over the past 30 years microwave photonics (MWP) has been defined as the field that study the interactions between microwave and optical waves and their applications in radar and communications system as well as in hybrid sensor‘s instrumentation. As said before software defined radio applications drive the technological development trough high speed\bandwidth and high dynamic range systems operating directly in the radio frequency domain. Nowadays, while digital electronics represent a limit on system performances, photonic technologies perfectly engages the today‘s system needs and offers promising solution thanks to its inherent high frequency and ultrawide bandwidth. Moreover photonic components with very high phase coherence guarantees highly stable microwave carriers; while strong immunity to the electromagnetic interference, low loss and high tunability make a MWP system robust, flexible and reliable. Historical research and development of MWP finds space in a wide range of applications including the generation, distribution and processing of radio frequency signals such as, for example, analog microwave photonic link, antenna remoting, high frequency and low noise photonic microwave signal generation, photonic microwave signal processing (true time delay for phased array systems, tunable high Q microwave photonic filter and high speed analog to digital converters) and broadband wireless access networks. Performances improvement of photonic and hybrid devices represents a key factor to improve the development of microwave photonic systems in many other applications such as Terahertz generation, optical packet switching and so on. Furthermore, advanced in silicon photonics and integration, makes the low cost complete microwave photonic system on chip just around the corner. In the last years the use of photonics has been suggested as an effective way for generating low phase-noise radio frequency carriers even at high frequency. However while a lot of efforts have been spent in the photonic generation of RF carriers, only few works have been presented on reconfigurable phase coding in the photonics-based signal generators. In this direction two innovative schemes for optically generate multifrequency direct RF phase modulated signals have been presented. Then we propose a wideband ADC with high precision and a photonic wireless receiver for sparse sensing. This dissertation focuses on microwave photonics for radar and telecommunications systems. In particular applications in the field of photonic RF signal generation, photonic analog to digital converters and photonic ultrawideband radio will be presented with the main objective to overcome the limitations of pure electrical systems. Schemes and results will be further detailed and discussed. The dissertation is organized as follows. In the first chapter an overview of the MWP technologies is presented, focusing the attention of the limits overcame by using hybrid optoelectronic systems in particular field of applications. Then optoelectronic devices are introduced in the second chapter to better understand their role in a MWP system. Chapters 3,4, and 5 present results on photonic microwave signal generation, photonic wideband analog to digital converters and photonic ultrawideband up\down converter for both radar and telecommunications applications. Finally in the chapter 6 an overview of the photonic radar prototype is given

Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors

University of Minnesota Ph.D. dissertation.November 2016. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); x, 137 pages.Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V

A Solid-State Phase Camera for Advanced Gravitational Wave Detectors

I present a novel way of wavefront sensing using a commercially available, continuouswavetime-of- ight camera with QVGA-resolution. This CMOS phase camera is capable of sensing externally modulated light sources with frequencies up to 100 MHz. The high-spatial-resolution of the sensor, combined with our integrated control electronics, allows the camera to image power modulation index as low as -62 dBc/second/pixel. The phase camera is applicable to problems where alignment and mode-mismatch sensing is needed and suited for diagnostic and control applications in gravitationalwave detectors. Specically, I explore the use of the phase camera in sensing the beat signals due to thermal distortions from point-like heat absorbers on the test masses in the Advanced LIGO detectors. The camera is capable of sensing optical path distortions greater than about two nanometers in the Advanced LIGO input mirrors, limited by the phase resolution. In homodyne readout, the performance can reach up to 0.1 nm, limited by the modulation amplitude sensitivity

External Cavity Mode-locked Semiconductor Lasers For The Generation Of Ultra-low Noise Multi-gigahertz Frequency Combs And Applications In Multi-heterodyne Detection Of Arbitrary Optical Waveforms

The construction and characterization of ultra-low noise semiconductor-based mode-locked lasers as frequency comb sources with multi-gigahertz combline-to-combline spacing is studied in this dissertation. Several different systems were built and characterized. The first of these systems includes a novel mode-locking mechanism based on phase modulation and periodic spectral filtering. This mode-locked laser design uses the same intra-cavity elements for both mode-locking and frequency stabilization to an intra-cavity, 1,000 Finesse, Fabry-Pérot Etalon (FPE). On a separate effort, a mode-locked laser based on a Slab-Coupled Optical Waveguide Amplifier (SCOWA) was built. This system generates a pulse-train with residual timing jitter o

Multi-band OFDM UWB receiver with narrowband interference suppression

A multi band orthogonal frequency division multiplexing (MB-OFDM) compatible ultra wideband (UWB) receiver with narrowband interference (NBI) suppression capability is presented. The average transmit power of UWB system is limited to -41.3 dBm/MHz in order to not interfere existing narrowband systems. Moreover, it must operate even in the presence of unintentional radiation of FCC Class-B compatible devices. If this unintentional radiation resides in the UWB band, it can jam the communication. Since removing the interference in digital domain requires higher dynamic range of analog front-end than removing it in analog domain, a programmable analog notch filter is used to relax the receiver requirements in the presence of NBI. The baseband filter is placed before the variable gain amplifier (VGA) in order to reduce the signal swing at the VGA input. The frequency hopping period of MB-OFDM puts a lower limit on the settling time of the filter, which is inverse proportional to notch bandwidth. However, notch bandwidth should be low enough not to attenuate the adjacent OFDM tones. Since these requirements are contradictory, optimization is needed to maximize overall performance. Two different NBI suppression schemes are tested. In the first scheme, the notch filter is operating for all sub-bands. In the second scheme, the notch filter is turned on during the sub-band affected by NBI. Simulation results indicate that the UWB system with the first and the second suppression schemes can handle up to 6 dB and 14 dB more NBI power, respectively. The results of this work are not limited to MB-OFDM UWB system, and can be applied to other frequency hopping systems

A GHz-range, High-resolution Multi-modulus Prescaler for Extreme Environment Applications

The generation of a precise, low-noise, reliable clock source is critical to developing mixed-signal and digital electronic systems. The applications of such a clock source are greatly expanded if the clock source can be configured to output different clock frequencies. The phase-locked loop (PLL) is a well-documented architecture for realizing this configurable clock source. Principle to the configurability of a PLL is a multi-modulus divider. The resolution of this divider (or prescaler) dictates the resolution of the configurable PLL output frequency. In integrated PLL designs, such a multi-modulus prescaler is usually sourced from a GHz-range voltage-controlled oscillator. Therefore, a fully-integrated PLL ASIC requires the development of a high-speed, high-resolution multi-modulus prescaler. The design challenges associated with developing such a prescaler are compounded when the application requires the device to operate in an extreme environment. In these extreme environments (often extra-terrestrial), wide temperature ranges and radiation effects can adversely affect the operation of electronic systems. Even more problematic is that extreme temperatures and ionizing radiation can cause permanent damage to electronic devices. Typical commercial-off-the-shelf (COTS) components are not able withstand such an environment, and any electronics operating in these extreme conditions must be designed to accommodate such operation. This dissertation describes the development of a high-speed, high-resolution, multi-modulus prescaler capable of operating in an extreme environment. This prescaler has been developed using current-mode logic (CML) on a 180-nm silicon-germanium (SiGe) BiCMOS process. The prescaler is capable of operating up to at least 5.4 GHz over a division range of 16-48 with a total of 27 configurable moduli. The prescaler is designed to provide excellent ionizing radiation hardness, single-event latch-up (SEL) immunity, and single-event upset (SEU) resistance over a temperature range of −180°C to 125°C