Super class AB RFC OTA with adaptive local common-mode feedback

A super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

Low-power OP-AMP operating in sub-threshold region with improved slew rate

This thesis focuses on the weak inversion design of low power low voltage Op-amp. The main objective of this thesis is to improve the slew rate of the Op-amp with a very less amount of power consumption. For this purpose, an adaptive bias circuit is used to improve the slew rate of an Op-amp in sub-threshold region by increasing the drain current of the input stage transistor of Op-amp under the dynamic condition instead increasing the quiescent current to reduce the power consumption. In this thesis we present sub-threshold Op-amp circuit with two different adaptive bias topology. First, an adaptive biased circuit with WTA (Winner Take All) topology, which is used in a class A Op-amp circuit and this circuit designed using UMC 180nm technology with a supply voltage of 0.8V. The second one is an adaptive bias circuit based on current subtractor topology, this topology is used in a class AB Op-amp circuit with supply voltage of ±0.6V. This thesis presents the comparison between Op-amp with adaptive bias (both topology) and without adaptive bias circuit