AN O-TREE FOR FLOORPLAN

ABSTRACT: Floorplanning is the process to arranging the number of blocks in to boundary. Conventionally different trees are used for Floorplanning. Here a new representation called O-Tree is used. This O-tree is the representation of admissible placement and used for Floorplanning. The admissible placement is to move blocks either left or bottom of the boundary and it reduces the white spaces in the Floorplanning. A deterministic algorithm will propose for the Floorplanning. This algorithm is generating from the O-Tree representation. The effectiveness of the proposed algorithm will be tested in MCNC benchmark suites

Accuracy Improvement of VLSI Floorplanning Based on Fuzzy Inference and GA/SA

Rapid increase of the scale of integration requires higher knowledge and well trained skills of experienced design engineers. However it is usually difficult for novice engineers to perform optimized design of initial and macroscopic placement in floorplanning. This paper proposes to apply the soft computing technology mostly fuzzy inference and genetic algorithms to automate the floorplanning design which decides a macroscopic placement of the top layer of LSI physical implementation. ISPD98 benchmark data is used for evaluation. The relation among several parameters of fuzzy inference and genetic algorithms and placement cost is discussed. The relation between I/O pins and the cost is also discussed. Simulated annealing is employed after genetic algorithms to avoid local optimization

Emerging Run-Time Reconfigurable FPGA and CAD Tools

Field-programmable gate array (FPGA) is a post fabrication reconfigurable device to accelerate domain specific computing systems. It offers offer high operation speed and low power consumption. However, the design flexibility and performance of FPGAs are severely constrained by the costly on-chip memories, e.g. static random access memory (SRAM) and FLASH memory. The objective of my dissertation is to explore the opportunity and enable the use of the emerging resistance random access memory (ReRAM) in FPGA design. The emerging ReRAM technology features high storage density, low access power consumption, and CMOS compatibility, making it a promising candidate for FPGA implementation. In particular, ReRAM has advantages of the fast access and nonvolatility, enabling the on-chip storage and access of configuration data. In this dissertation, I first propose a novel three-dimensional stacking scheme, namely, high-density interleaved memory (HIM). The structure improves the density of ReRAM meanwhile effectively reducing the signal interference induced by sneak paths in crossbar arrays. To further enhance the access speed and design reliability, a fast sensing circuit is also presented which includes a new sense amplifier scheme and reference cell configuration. The proposed ReRAM FPGA leverages a similar architecture as conventional SRAM based FPGAs but utilizes ReRAM technology in all component designs. First, HIM is used to implement look-up table (LUT) and block random access memories (BRAMs) for func- tionality process. Second, a 2R1T, two ReRAM cells and one transistor, nonvolatile switch design is applied to construct connection blocks (CBs) and switch blocks (SBs) for signal transition. Furthermore, unified BRAM (uBRAM) based on the current BRAM architecture iv is introduced, offering both configuration and temporary data storage. The uBRAMs provides extremely high density effectively and enlarges the FPGA capacity, potentially saving multiple contexts of configuration. The fast configuration scheme from uBRAM to logic and routing components also makes fast run-time partial reconfiguration (PR) much easier, improving the flexibility and performance of the entire FPGA system. Finally, modern place and route tools are designed for homogeneous fabric of FPGA. The PR feature, however, requires the support of heterogeneous logic modules in order to differentiate PR modules from static ones and therefore maintain the signal integration. The existing approaches still reply on designers’ manual effort, which significantly prolongs design time and lowers design efficiency. In this dissertation, I integrate PR support into VPR – an academic place and route tool by introducing a B*-tree modular placer (BMP) and PR-aware router. As such, users are able to explore new architectures or map PR applications to a variety of FPGAs. More importantly, this enhanced feature can also support fast design automation, e.g. mapping IP core, loading pre-synthesizing logic modules, etc

An optimal algorithm for floorplan area optimization

[[abstract]]An optimal algorithm for the VLSI floorplan area optimization problem is presented. The algorithm is an extension of the technique described by L. Stockmeyer (Information and Control, Vol. 59, pp. 91-101, 1983). Experimental results indicate that this algorithm pruned a very large number of redundant implementations. In addition, since the algorithm basically exploits the geometric property of the topology of the given floorplan, it does not need to depend on the polar dual graphs to calculate the longest paths. Consequently, it is able to run more efficiently than the branch-and-bound algorithm.[[fileno]]2030229030014[[department]]資訊工程學