Microchip Analysis of Temperature and Humidity’s Effect on the Performance of Supply Voltage and Age

Semiconductor chips are commonly duplicated overseas and sold on the black market, which causes product failures worldwide and diminishes the reputation of the companies involved in the supply chain. Currently, companies use a burn-in test: this test involves equipment that is used to test and evaluate high power chips, boards, or products. This prevents defective chips from being incorporated into any finished devices. While this method is quite common, the process will never eliminate the possibility of failed chips. Some are random and cannot be traced back to their failure cause. This research aims to determine how temperature and humidity affects a microchip at its different stages of life. This project will use a DOE, Design of Experiments, Analysis to determine the trend between temperature, humidity, VCC, chip-to-chip variation, age and how it affects, VOH, VOL, VIH, VIL, and power consumption. To test the hypothesis that an older chip leads to more failures and particular environment can detect a defective chip based on the input conditions of temperature, humidity, VCC, chip-to-chip variation, and age, this research will design an autonomous environment that will reduce the amount of failed chips that are used in production. The system will adjust and maintain the temperature and humidity of a chamber where the microchip will be tested. The chamber read accurately and precisely as well as the microchip voltage inputs and outputs. These results suggest that all values of VOH, VOL, VIH, VIL, and power consumption can be read, calculated, and recorded onto a DOE Analysis excel sheet to observe the results and produce the required graphs of temperature and humidity vs VOH, VOL, VIH, VIL, and power consumption

Effects of Temperature, Humidity, and Supply Voltage on MSP430 Behaviors

As the demand for microchips to control a more technologically connected world increases, so does the outsourcing of manufacturing these microchips, which poses risks of old microchips being refurbished as new and new microchips being tampered with Hardware Trojans (HT). The purpose of this research is to develop a systematic testing approach to analyze various microchips for abnormal behaviors. The Design of Experiments (DOE) technique was used to investigate the effects of temperature, humidity, and supply voltage (VCC) on microchip response parameters of VOL, VOH, VIL, VIH, and power consumption values. All these parameters were also individually examined against supply voltage under various temperature and humidity conditions on ten different MSP430FG6626s in 2 separate tests to determine Chip to Chip (C-2-C) variation, microchip defects and potential failures. A sealed enclosure was created to achieve various needed testing conditions and to allow for multiple chips to be tested simultaneously. Corresponding devices were equipped to the enclosure for in-situ input variation and output recording. DOE analysis concluded that supply voltage is the most statistically significant factor affecting key microchip response parameters of VIL, VIH and VOH within the limits of the input factors. The high repeatability and consistency of the response data to supply voltage ramping among the tested chips confirm that the testing setup and method used in this research are valid for screening microchips for defects and irregularities

DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans

The global semiconductor supply chain involves design and fabrication at various locations, which leads to multiple security vulnerabilities, e.g., Hardware Trojan (HT) insertion. Although most HTs target digital circuits, HTs can be inserted in analog circuits. Therefore, several techniques have been developed for HT insertions in analog circuits. Capacitance-based Analog Hardware Trojan (AHT) is one of the stealthiest HT that can bypass most existing HT detection techniques because it uses negligible charge accumulation in the capacitor to generate stealthy triggers. To address the charge sharing and accumulation issues, we propose a novel way to detect such capacitance-based AHT in this paper. Secondly, we critically analyzed existing AHTs to highlight their respective limitations. We proposed a stealthier capacitor-based AHT (fortified AHT) that can bypass our novel AHT detection technique by addressing these limitations. Finally, by critically analyzing the proposed fortified AHT and existing AHTs, we developed a robust two-phase framework (DeMiST) in which a synchronous system can mitigate the effects of capacitance-based stealthy AHTs by turning off the triggering capability of AHT. In the first phase, we demonstrate how the synchronous system can avoid the AHT during run-time by controlling the supply voltage of the intermediate combinational circuits. In the second phase, we proposed a supply voltage duty cycle-based validation technique to detect capacitance-based AHTs. Furthermore, DeMiST amplified the switching activity for charge accumulation to such a degree that it can be easily detectable using existing switching activity-based HT detection techniques.Comment: Accepted at ACM Hardware and Architectural Support for Security and Privacy (HASP) 202

An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification

International audienceThis paper introduces an embedded solution for the detection of hardware trojans (HTs) and counterfeits. The proposed method, which considers that HTs are necessarily inserted on production lots and not on a single device, is based on the fingerprinting of the static distribution of the supply voltage (V dd) over the whole surface of an integrated circuit. The measurement of this fingerprint is done through an array of sensors sensitive to the local V dd value and fingerprint extraction is based on a novel variation model of CMOS logic performance. This model takes into account not only process variations but also the impact of the design (layout, supply routing, and so on). In addition to the fingerprinting process, this paper introduces an adaptive distinguisher to deal with the difficult problem of fixing the p-value on large sets of statistical tests. The efficiency of the whole detection methodology is experimentally demonstrated on a set of 24 FPGA boards