80 research outputs found

    Techniques for Improving Security and Trustworthiness of Integrated Circuits

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    The integrated circuit (IC) development process is becoming increasingly vulnerable to malicious activities because untrusted parties could be involved in this IC development flow. There are four typical problems that impact the security and trustworthiness of ICs used in military, financial, transportation, or other critical systems: (i) Malicious inclusions and alterations, known as hardware Trojans, can be inserted into a design by modifying the design during GDSII development and fabrication. Hardware Trojans in ICs may cause malfunctions, lower the reliability of ICs, leak confidential information to adversaries or even destroy the system under specifically designed conditions. (ii) The number of circuit-related counterfeiting incidents reported by component manufacturers has increased significantly over the past few years with recycled ICs contributing the largest percentage of the total reported counterfeiting incidents. Since these recycled ICs have been used in the field before, the performance and reliability of such ICs has been degraded by aging effects and harsh recycling process. (iii) Reverse engineering (RE) is process of extracting a circuit’s gate-level netlist, and/or inferring its functionality. The RE causes threats to the design because attackers can steal and pirate a design (IP piracy), identify the device technology, or facilitate other hardware attacks. (iv) Traditional tools for uniquely identifying devices are vulnerable to non-invasive or invasive physical attacks. Securing the ID/key is of utmost importance since leakage of even a single device ID/key could be exploited by an adversary to hack other devices or produce pirated devices. In this work, we have developed a series of design and test methodologies to deal with these four challenging issues and thus enhance the security, trustworthiness and reliability of ICs. The techniques proposed in this thesis include: a path delay fingerprinting technique for detection of hardware Trojans, recycled ICs, and other types counterfeit ICs including remarked, overproduced, and cloned ICs with their unique identifiers; a Built-In Self-Authentication (BISA) technique to prevent hardware Trojan insertions by untrusted fabrication facilities; an efficient and secure split manufacturing via Obfuscated Built-In Self-Authentication (OBISA) technique to prevent reverse engineering by untrusted fabrication facilities; and a novel bit selection approach for obtaining the most reliable bits for SRAM-based physical unclonable function (PUF) across environmental conditions and silicon aging effects

    Effects of Temperature, Humidity, and Supply Voltage on MSP430 Behaviors

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    As the demand for microchips to control a more technologically connected world increases, so does the outsourcing of manufacturing these microchips, which poses risks of old microchips being refurbished as new and new microchips being tampered with Hardware Trojans (HT). The purpose of this research is to develop a systematic testing approach to analyze various microchips for abnormal behaviors. The Design of Experiments (DOE) technique was used to investigate the effects of temperature, humidity, and supply voltage (VCC) on microchip response parameters of VOL, VOH, VIL, VIH, and power consumption values. All these parameters were also individually examined against supply voltage under various temperature and humidity conditions on ten different MSP430FG6626s in 2 separate tests to determine Chip to Chip (C-2-C) variation, microchip defects and potential failures. A sealed enclosure was created to achieve various needed testing conditions and to allow for multiple chips to be tested simultaneously. Corresponding devices were equipped to the enclosure for in-situ input variation and output recording. DOE analysis concluded that supply voltage is the most statistically significant factor affecting key microchip response parameters of VIL, VIH and VOH within the limits of the input factors. The high repeatability and consistency of the response data to supply voltage ramping among the tested chips confirm that the testing setup and method used in this research are valid for screening microchips for defects and irregularities

    Microchip Analysis of Temperature and Humidity’s Effect on the Performance of Supply Voltage and Age

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    Semiconductor chips are commonly duplicated overseas and sold on the black market, which causes product failures worldwide and diminishes the reputation of the companies involved in the supply chain. Currently, companies use a burn-in test: this test involves equipment that is used to test and evaluate high power chips, boards, or products. This prevents defective chips from being incorporated into any finished devices. While this method is quite common, the process will never eliminate the possibility of failed chips. Some are random and cannot be traced back to their failure cause. This research aims to determine how temperature and humidity affects a microchip at its different stages of life. This project will use a DOE, Design of Experiments, Analysis to determine the trend between temperature, humidity, VCC, chip-to-chip variation, age and how it affects, VOH, VOL, VIH, VIL, and power consumption. To test the hypothesis that an older chip leads to more failures and particular environment can detect a defective chip based on the input conditions of temperature, humidity, VCC, chip-to-chip variation, and age, this research will design an autonomous environment that will reduce the amount of failed chips that are used in production. The system will adjust and maintain the temperature and humidity of a chamber where the microchip will be tested. The chamber read accurately and precisely as well as the microchip voltage inputs and outputs. These results suggest that all values of VOH, VOL, VIH, VIL, and power consumption can be read, calculated, and recorded onto a DOE Analysis excel sheet to observe the results and produce the required graphs of temperature and humidity vs VOH, VOL, VIH, VIL, and power consumption

    Novel Computational Methods for Integrated Circuit Reverse Engineering

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    Production of Integrated Circuits (ICs) has been largely strengthened by globalization. System-on-chip providers are capable of utilizing many different providers which can be responsible for a single task. This horizontal structure drastically improves to time-to-market and reduces manufacturing cost. However, untrust of oversea foundries threatens to dismantle the complex economic model currently in place. Many Intellectual Property (IP) consumers become concerned over what potentially malicious or unspecified logic might reside within their application. This logic which is inserted with the intention of causing harm to a consumer has been referred to as a Hardware Trojan (HT). To help IP consumers, researchers have looked into methods for finding HTs. Such methods tend to rely on high-level information relating to the circuit, which might not be accessible. There is a high possibility that IP is delivered in the gate or layout level. Some services and image processing methods can be leveraged to convert layout level information to gate-level, but such formats are incompatible with detection schemes that require hardware description language. By leveraging standard graph and dynamic programming algorithms a set of tools is developed that can help bridge the gap between gate-level netlist access and HT detection. To help in this endeavor this dissertation focuses on several problems associated with reverse engineering ICs. Logic signal identification is used to find malicious signals, and logic desynthesis is used to extract high level details. Each of the proposed method have their results analyzed for accuracy and runtime. It is found that method for finding logic tends to be the most difficult task, in part due to the degree of heuristic\u27s inaccuracy. With minor improvements moderate sized ICs could have their high-level function recovered within minutes, which would allow for a trained eye or automated methods to more easily detect discrepancies within a circuit\u27s design

    DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans

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    The global semiconductor supply chain involves design and fabrication at various locations, which leads to multiple security vulnerabilities, e.g., Hardware Trojan (HT) insertion. Although most HTs target digital circuits, HTs can be inserted in analog circuits. Therefore, several techniques have been developed for HT insertions in analog circuits. Capacitance-based Analog Hardware Trojan (AHT) is one of the stealthiest HT that can bypass most existing HT detection techniques because it uses negligible charge accumulation in the capacitor to generate stealthy triggers. To address the charge sharing and accumulation issues, we propose a novel way to detect such capacitance-based AHT in this paper. Secondly, we critically analyzed existing AHTs to highlight their respective limitations. We proposed a stealthier capacitor-based AHT (fortified AHT) that can bypass our novel AHT detection technique by addressing these limitations. Finally, by critically analyzing the proposed fortified AHT and existing AHTs, we developed a robust two-phase framework (DeMiST) in which a synchronous system can mitigate the effects of capacitance-based stealthy AHTs by turning off the triggering capability of AHT. In the first phase, we demonstrate how the synchronous system can avoid the AHT during run-time by controlling the supply voltage of the intermediate combinational circuits. In the second phase, we proposed a supply voltage duty cycle-based validation technique to detect capacitance-based AHTs. Furthermore, DeMiST amplified the switching activity for charge accumulation to such a degree that it can be easily detectable using existing switching activity-based HT detection techniques.Comment: Accepted at ACM Hardware and Architectural Support for Security and Privacy (HASP) 202

    Quantifiable Assurance: From IPs to Platforms

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    Hardware vulnerabilities are generally considered more difficult to fix than software ones because they are persistent after fabrication. Thus, it is crucial to assess the security and fix the vulnerabilities at earlier design phases, such as Register Transfer Level (RTL) and gate level. The focus of the existing security assessment techniques is mainly twofold. First, they check the security of Intellectual Property (IP) blocks separately. Second, they aim to assess the security against individual threats considering the threats are orthogonal. We argue that IP-level security assessment is not sufficient. Eventually, the IPs are placed in a platform, such as a system-on-chip (SoC), where each IP is surrounded by other IPs connected through glue logic and shared/private buses. Hence, we must develop a methodology to assess the platform-level security by considering both the IP-level security and the impact of the additional parameters introduced during platform integration. Another important factor to consider is that the threats are not always orthogonal. Improving security against one threat may affect the security against other threats. Hence, to build a secure platform, we must first answer the following questions: What additional parameters are introduced during the platform integration? How do we define and characterize the impact of these parameters on security? How do the mitigation techniques of one threat impact others? This paper aims to answer these important questions and proposes techniques for quantifiable assurance by quantitatively estimating and measuring the security of a platform at the pre-silicon stages. We also touch upon the term security optimization and present the challenges for future research directions

    ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance

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    The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Packing more transistors on a monolithic IC at each node becomes more difficult and expensive. Companies in the semiconductor industry are increasingly seeking technological solutions to close the gap and enhance cost-performance while providing more functionality through integration. Putting all of the operations on a single chip (known as a system on a chip, or SoC) presents several issues, including increased prices and greater design complexity. Heterogeneous integration (HI), which uses advanced packaging technology to merge components that might be designed and manufactured independently using the best process technology, is an attractive alternative. However, although the industry is motivated to move towards HI, many design and security challenges must be addressed. This paper presents a three-tier security approach for secure heterogeneous integration by investigating supply chain security risks, threats, and vulnerabilities at the chiplet, interposer, and system-in-package levels. Furthermore, various possible trust validation methods and attack mitigation were proposed for every level of heterogeneous integration. Finally, we shared our vision as a roadmap toward developing security solutions for a secure heterogeneous integration
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