8 research outputs found
Simulation and Synthesis of Efficient Majority Logic Fault Detector Using EG-LDPC Codes to Reduce Access Time for Memory Applications
This paper presents an error-detection method for Euclidean Geometry low density parity check codes with majority logic decoding methodology in VHDL language and the output is verified with the help of Xilinx12.1. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. Starting from the original design of the ML decoder introduced, the proposed ML Detector/Decoder (MLDD) has been implemented using the Euclidean Geometry low density parity check codes. The proposed improved majority logic detector/decoder to perform data error correction in simple way using additional error correction technique and also reducing the delay time by detecting the errors in parallel manner. Hence the decoding process uses less number of cycles which reduces the delay
Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware
This paper addresses the problem of designing LDPC decoders robust to
transient errors introduced by a faulty hardware. We assume that the faulty
hardware introduces errors during the message passing updates and we propose a
general framework for the definition of the message update faulty functions.
Within this framework, we define symmetry conditions for the faulty functions,
and derive two simple error models used in the analysis. With this analysis, we
propose a new interpretation of the functional Density Evolution threshold
previously introduced, and show its limitations in case of highly unreliable
hardware. However, we show that under restricted decoder noise conditions, the
functional threshold can be used to predict the convergence behavior of FAIDs
under faulty hardware. In particular, we reveal the existence of robust and
non-robust FAIDs and propose a framework for the design of robust decoders. We
finally illustrate robust and non-robust decoders behaviors of finite length
codes using Monte Carlo simulations.Comment: 30 pages, submitted to IEEE Transactions on Communication
Density Evolution and Functional Threshold for the Noisy Min-Sum Decoder
This paper investigates the behavior of the Min-Sum decoder running on noisy
devices. The aim is to evaluate the robustness of the decoder in the presence
of computation noise, e.g. due to faulty logic in the processing units, which
represents a new source of errors that may occur during the decoding process.
To this end, we first introduce probabilistic models for the arithmetic and
logic units of the the finite-precision Min-Sum decoder, and then carry out the
density evolution analysis of the noisy Min-Sum decoder. We show that in some
particular cases, the noise introduced by the device can help the Min-Sum
decoder to escape from fixed points attractors, and may actually result in an
increased correction capacity with respect to the noiseless decoder. We also
reveal the existence of a specific threshold phenomenon, referred to as
functional threshold. The behavior of the noisy decoder is demonstrated in the
asymptotic limit of the code-length -- by using "noisy" density evolution
equations -- and it is also verified in the finite-length case by Monte-Carlo
simulation.Comment: 46 pages (draft version); extended version of the paper with same
title, submitted to IEEE Transactions on Communication
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An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes
In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e., the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at [email protected]