2,925 research outputs found
A Systematic Approach to Constructing Incremental Topology Control Algorithms Using Graph Transformation
Communication networks form the backbone of our society. Topology control
algorithms optimize the topology of such communication networks. Due to the
importance of communication networks, a topology control algorithm should
guarantee certain required consistency properties (e.g., connectivity of the
topology), while achieving desired optimization properties (e.g., a bounded
number of neighbors). Real-world topologies are dynamic (e.g., because nodes
join, leave, or move within the network), which requires topology control
algorithms to operate in an incremental way, i.e., based on the recently
introduced modifications of a topology. Visual programming and specification
languages are a proven means for specifying the structure as well as
consistency and optimization properties of topologies. In this paper, we
present a novel methodology, based on a visual graph transformation and graph
constraint language, for developing incremental topology control algorithms
that are guaranteed to fulfill a set of specified consistency and optimization
constraints. More specifically, we model the possible modifications of a
topology control algorithm and the environment using graph transformation
rules, and we describe consistency and optimization properties using graph
constraints. On this basis, we apply and extend a well-known constructive
approach to derive refined graph transformation rules that preserve these graph
constraints. We apply our methodology to re-engineer an established topology
control algorithm, kTC, and evaluate it in a network simulation study to show
the practical applicability of our approachComment: This document corresponds to the accepted manuscript of the
referenced journal articl
Applying Formal Methods to Networking: Theory, Techniques and Applications
Despite its great importance, modern network infrastructure is remarkable for
the lack of rigor in its engineering. The Internet which began as a research
experiment was never designed to handle the users and applications it hosts
today. The lack of formalization of the Internet architecture meant limited
abstractions and modularity, especially for the control and management planes,
thus requiring for every new need a new protocol built from scratch. This led
to an unwieldy ossified Internet architecture resistant to any attempts at
formal verification, and an Internet culture where expediency and pragmatism
are favored over formal correctness. Fortunately, recent work in the space of
clean slate Internet design---especially, the software defined networking (SDN)
paradigm---offers the Internet community another chance to develop the right
kind of architecture and abstractions. This has also led to a great resurgence
in interest of applying formal methods to specification, verification, and
synthesis of networking protocols and applications. In this paper, we present a
self-contained tutorial of the formidable amount of work that has been done in
formal methods, and present a survey of its applications to networking.Comment: 30 pages, submitted to IEEE Communications Surveys and Tutorial
Combining k-Induction with Continuously-Refined Invariants
Bounded model checking (BMC) is a well-known and successful technique for
finding bugs in software. k-induction is an approach to extend BMC-based
approaches from falsification to verification. Automatically generated
auxiliary invariants can be used to strengthen the induction hypothesis. We
improve this approach and further increase effectiveness and efficiency in the
following way: we start with light-weight invariants and refine these
invariants continuously during the analysis. We present and evaluate an
implementation of our approach in the open-source verification-framework
CPAchecker. Our experiments show that combining k-induction with
continuously-refined invariants significantly increases effectiveness and
efficiency, and outperforms all existing implementations of k-induction-based
software verification in terms of successful verification results.Comment: 12 pages, 5 figures, 2 tables, 2 algorithm
Analog Property Checkers: A Ddr2 Case Study
The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems.
In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach
Solving the bank with Rebel: on the design of the Rebel specification language and its application inside a bank
Large organizations like banks suffer from the ever growing complexity of their systems. Evolving the software becomes harder and harder since a single change can affect a much larger part of the system than predicted upfront. A large contributing factor to this problem is that the actual domain knowledge is often implicit, incomplete, or out of date, making it difficult to reason about the correct behavior of the system as a whole. With Rebel we aim to capture and centralize the domain knowledge and relate it to the running systems. Rebel is a formal specification language for controlling the intrinsic complexity of software for financial enterprise systems. In collaboration with ING, a large Dutch bank, we developed the Rebel specification language and an Integrated Specification Environment (ISE), currently offering automated simulation and checking of Rebel specifications using a Satisfiability Modulo Theories (SMT) solver. In this paper we report on our design choices for Rebel, the implementation and features of the ISE, and our initial observations on the application of Rebel inside the bank
10161 Abstracts Collection -- Decision Procedures in Software, Hardware and Bioware
From April 19th, 2010 to April 23rd, 2010, the Dagstuhl Seminar 10161
"Decision Procedures in Soft, Hard and Bio-ware"
was held in Schloss Dagstuhl Leibniz Center for Informatics.
During the seminar, several participants presented their current research,
and ongoing work and open problems were discussed. Abstracts of the
presentations given during the seminar as well as links to slides and links to
papers behind the presentations and papers produced as a result
of the seminar are put together in this paper. The first section describes
the seminar topics and goals in general. Links to extended abstracts or
full papers are provided, if available
SAT-based Explicit LTL Reasoning
We present here a new explicit reasoning framework for linear temporal logic
(LTL), which is built on top of propositional satisfiability (SAT) solving. As
a proof-of-concept of this framework, we describe a new LTL satisfiability
tool, Aalta\_v2.0, which is built on top of the MiniSAT SAT solver. We test the
effectiveness of this approach by demonnstrating that Aalta\_v2.0 significantly
outperforms all existing LTL satisfiability solvers. Furthermore, we show that
the framework can be extended from propositional LTL to assertional LTL (where
we allow theory atoms), by replacing MiniSAT with the Z3 SMT solver, and
demonstrating that this can yield an exponential improvement in performance
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