Survey of partitioning techniques in silicon compilation

In the silicon compilation design process, partitioning is usually the first problem to be investigated because partitioning algorithms form the backbone of many algorithms including: system synthesis, processor synthesis, floorplanning, and placement. In this survey, several partitioning techniques will be examined. In addition, this paper will review the partitioning algorithms used by synthesis systems at different design levels

Chromosome mapping: radiation hybrid data and stochastic spin models

This work approaches human chromosome mapping by developing algorithms for ordering markers associated with radiation hybrid data. Motivated by recent work of Boehnke et al. [1], we formulate the ordering problem by developing stochastic spin models to search for minimum-break marker configurations. As a particular application, the methods developed are applied to 14 human chromosome-21 markers tested by Cox et al. [2]. The methods generate configurations consistent with the best found by others. Additionally, we find that the set of low-lying configurations is described by a Markov-like ordering probability distribution. The distribution displays cluster correlations reflecting closely linked loci.Comment: 26 Pages, uuencoded LaTex, Submitted to Phys. Rev. E, [email protected], [email protected]

A hybrid shifting bottleneck-tabu search heuristic for the job shop total weighted tardiness problem

In this paper, we study the job shop scheduling problem with the objective of minimizing the total weighted tardiness. We propose a hybrid shifting bottleneck - tabu search (SB-TS) algorithm by replacing the reoptimization step in the shifting bottleneck (SB) algorithm by a tabu search (TS). In terms of the shifting bottleneck heuristic, the proposed tabu search optimizes the total weighted tardiness for partial schedules in which some machines are currently assumed to have infinite capacity. In the context of tabu search, the shifting bottleneck heuristic features a long-term memory which helps to diversify the local search. We exploit this synergy to develop a state-of-the-art algorithm for the job shop total weighted tardiness problem (JS-TWT). The computational effectiveness of the algorithm is demonstrated on standard benchmark instances from the literature

Instruction fetch architectures and code layout optimizations

The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing a higher performance processor implies balancing all the pipeline stages to ensure that overall performance is not dominated by any of them. This means that a faster execution engine also requires a faster fetch engine, to ensure that it is possible to read and decode enough instructions to keep the pipeline full and the functional units busy. This paper explores the challenges faced by the instruction fetch stage for a variety of processor designs, from early pipelined processors, to the more aggressive wide issue superscalars. We describe the different fetch engines proposed in the literature, the performance issues involved, and some of the proposed improvements. We also show how compiler techniques that optimize the layout of the code in memory can be used to improve the fetch performance of the different engines described Overall, we show how instruction fetch has evolved from fetching one instruction every few cycles, to fetching one instruction per cycle, to fetching a full basic block per cycle, to several basic blocks per cycle: the evolution of the mechanism surrounding the instruction cache, and the different compiler optimizations used to better employ these mechanisms.Peer ReviewedPostprint (published version

A tabu search algorithm for scheduling a single robot in a job-shop environment

We consider a single-machine scheduling problem which arises as a subproblem in a job-shop environment where the jobs have to be transported between the machines by a single transport robot. The robot scheduling problem may be regarded as a generalization of the travelling-salesman problem with time windows, where additionally generalized precedence constraints have to be respected. The objective is to determine a sequence of all nodes and corresponding starting times in the given time windows in such a way that all generalized precedence relations are respected and the sum of all travelling and waiting times is minimized. We present a local search algorithm for this problem where an appropriate neighborhood structure is defined using problem-specific properties. In order to make the search process more efficient, we apply some techniques which accelerate the evaluation of the solutions in the proposed neighbourhood considerably. Computational results are presented for test data arising from job-shop instances with a single transport robot

Application of shape grammar theory to underground rail station design and passenger evacuation

This paper outlines the development of a computer design environment that generates station ‘reference’ plans for analysis by designers at the project feasibility stage. The developed program uses the theoretical concept of shape grammar, based upon principles of recognition and replacement of a particular shape to enable the generation of station layouts. The developed novel shape grammar rules produce multiple plans of accurately sized infrastructure faster than by traditional means. A finite set of station infrastructure elements and a finite set of connection possibilities for them, directed by regulations and the logical processes of station usage, allows for increasingly complex composite shapes to be automatically produced, some of which are credible station layouts at ‘reference’ block plan level. The proposed method of generating shape grammar plans is aligned to London Underground standards, in particular to the Station Planning Standards and Guidelines 5th edition (SPSG5 2007) and the BS-7974 fire safety engineering process. Quantitative testing is via existing evacuation modelling software. The prototype system, named SGEvac, has both the scope and potential for redevelopment to any other country’s design legislation